search for: copytoreg

Displaying 20 results from an estimated 169 matches for "copytoreg".

2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...64 t15: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<1>, Constant:i64<2>, Constant:i64<3>, Constant:i64<4>, Constant:i64<5>, Constant:i64<6>, Constant:i64<7> t16: v8i64 = add t7, t15 t18: ch = CopyToReg t0, Register:v8i64 %vreg16, t16 t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5 t22: i64 = AssertSext t20, ValueType:ch:i8 t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0> t24: v8i64 = ve...
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
...s the problem. t0: ch = EntryToken t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0 t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2 t13: ch = CopyToReg t0, Register:i64 %vreg1, t4 t15: ch = CopyToReg t0, Register:i64 %vreg2, t8 t26: ch = TokenFactor t11, t13, t15, t2:1, t4:1, t6:1, t8:1 t16: i64 = sdiv t2, t4 Before legalization, there is a single sdiv node. After legaliz...
2016 Aug 23
2
Help in understanding physreg LiveVariables
So if I first create the value in an entry BB and then build a CopyToReg but then I have to read it in a BB that loops back to itself, with it's own CopyToReg at the end, then I have two CopyToReg nodes for the same value. In this case, I need to create 3 virt regs, 1 for each CopyToReg and a third for the CopyFromReg in the beginning of the loop BB, right? And then...
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
Well, that's the thing: I thought that was CopyToReg. I don't know what the name of the node is to load one value into a register, so I don't know how to construct such a pattern. On Sat, Nov 4, 2017 at 9:23 PM Craig Topper <craig.topper at gmail.com> wrote: > Do you have a pattern for loading an i16 immediate into a 16-bit registe...
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
...arget triple = "tms9900" ; Function Attrs: noinline nounwind optnone define signext i16 @my_func() #0 { entry: ret i16 127 } ------- debug output -------- Optimized legalized selection DAG: BB#0 'my_func:entry' SelectionDAG has 5 nodes: t0: ch = EntryToken t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127> t4: ch = TMS9900ISD::Ret t3, Register:i16 %R5, t3:1 ===== Instruction selection begins: BB#0 'entry' Selecting: t4: ch = TMS9900ISD::Ret t3, Register:i16 %R5, t3:1 ISEL: Starting pattern match on root node: t4: ch = TMS9900ISD::Ret t3, Regis...
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
So there's a DAG that looks like this in the debug output: Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127> In the instruction selection phase, what pattern would that match? I've constructed this so far: (??? REG16:$dst, i16imm:$src) but the problem is, I can't determine what to use as ???. There is an ISD::CopyToReg enum value, but I don't...
2020 Feb 22
2
COPYs between register classes
...egers is GRX32, which also contains the high 32-bit part registers. I have tried to find a simple way to constrain the register class of such copies (also at -O0), but this turned out to not be quite simple. Just selecting a pseudo instruction with a custom inserter does not seem to work since CopyToReg/CopyFromReg have special handlings in InstrEmitter. I then tried in SystemZDAGToDAG.cpp to select a CopyToReg to (CopyToReg COPY_TO_REGCLASS), which worked fine. But I could not get the same results with CopyFromReg. (COPY_TO_REGCLASS CopyFromReg) only resulted in a later COPY into GR32, bu...
2015 Jan 27
4
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
I have a CopyToReg that is moving a 16bit reg to a 32bit reg, it's currently being mapped out as a simple mov (not an ext), I would like to change that to an ext. It seemed that the SelDAG was the easiest and cleanest way to do this. I can change the mov to an extension MI in the .td file; however, I can't t...
2015 Jan 27
2
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
I have a CopyToReg that is copying from different size types, what's the best way to change that to a zext or sext node based on signed or unsigned? I'm fairly unfamiliar with SelectionDAG process (outside of the docs on llvm website). It seems like I should be able to insert a custom hook using the registe...
2018 Feb 16
0
CopyToReg node
Hi all, I'm having some trouble with x86 generating some CopyToReg nodes with a null 2nd operand. I've done an extensive search of the entire codebase and found that all creation of CopyToReg nodes happens at SelectionDAG.h, eventually, but my debug messages did not register a call to either of the three getCopyToReg methods it provides. Is there any other pla...
2006 May 30
2
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
I have changed the way in which the ARM backend generates a function return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch is attached. In my opinion the resulting code is easier to understand, but I have some questions: Why all backends use RETFLAG? Why it is named RETFLAG? Why the Copy that places the result must have a Fla...
2015 Jan 27
2
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
...om a narrower type. Can you elaborate how I could use these to help? Again, I'm pretty unfamiliar with the SDNodes. Thanks. On Tue, Jan 27, 2015 at 3:22 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 01/27/2015 12:16 PM, Ryan Taylor wrote: > > I have a CopyToReg that is copying from different size types, what's the > best way to change that to a zext or sext node based on signed or unsigned? > > I'm fairly unfamiliar with SelectionDAG process (outside of the docs on > llvm website). > > It seems like I should be able to insert a...
2018 May 30
2
InstrEmitter::CreateVirtualRegisters handling of CopyToReg
...r.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -243,18 +243,21 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,      if (!VRBase && !IsClone && !IsCloned)        for (SDNode *User : Node->uses()) {          if (User->getOpcode() == ISD::CopyToReg &&              User->getOperand(2).getNode() == Node &&              User->getOperand(2).getResNo() == i) {            unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();            if (TargetRegisterInfo::isVirtualRegister(Reg)) { -          ...
2016 Aug 23
2
Help in understanding physreg LiveVariables
So if I create a value with a DAG.getUndef(myVT); call during instruction legalization, how can I access that value as input in another BB/DAG (also during instruction legalization) without worrying about live-ins and/or phi nodes? Can I create a single virtual register and build both a CopyToReg and a CopyFromReg node with it? I assumed that would break SSA. Perhaps I should have said that what stops me is that I don't know how to pass a newly created virtual register from one MBB/DAG to another. Tyler From: Matthias Braun <mbraun at apple.com> To: Tyler Kenney/Marl...
2007 Oct 17
2
[LLVMdev] The one remaining bug keeping CellSPU from release...
Evan: What you requested was in the debug output (sans offending Node), but here it is, outside of the attachment. The offending node is highlighted: SU(0): 0xa908760: ch = EntryToken SU(1): 0xa907600: i32,ch,flag = CopyFromReg 0xa9095d0, 0xa9070e0, 0xa9095d0:1 0xa906e30: ch,flag = CopyToReg 0xa908760, 0xa9070e0, 0xa9071f0 <<--<<--<<--<<--<< Node 0xa9095d0: ch,flag = inlineasm 0xa906e30, 0xa908570, 0xa908c60, 0xa9070e0, 0xa9075a0, 0xa9070e0, 0xa906e30:1 SU(2): 0xa909560: ch = CopyToReg 0xa907600:1, 0xa909500, 0xa907600 SU(3): 0xa907ff0: ch = BRZ 0...
2012 Dec 09
0
[LLVMdev] PHI instructions without CopyFromReg/CopyToReg
In my target I want to have mem-mem operations. But PHI instructions use virtual registers and gets converted to a series of CopyFromReg and CopyToReg instructions. These DAGs end up using physical registers. My first approach was to spill the virtual register to force a mem-mem operation. But I was unable to do this using LowerOperation() and setOperationAction(ISD::CopyToReg, MVT::i32, Custom); Any ideas would be appreciated. Is there a way...
2006 May 30
0
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
On Tue, 30 May 2006, [UTF-8] Rafael Esp?ndola wrote: > I have changed the way in which the ARM backend generates a function > return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now > expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch > is attached. Ok, I haven't looked at the code, but you're free to do whatever make sense. > In my opinion the resulting code is easier to understand, but I have > some questions: &g...
2007 Oct 18
0
[LLVMdev] The one remaining bug keeping CellSPU from release...
Sorry, still not enough information. I am guessing it's asserting in getVR() called from EmitNode()? The node is CopyToReg and it's trying to find the virtual register of operand 2? From the schedule, I don't see the definition of the operand. Can you do DAG.viewGraph()? That should gives us a better idea. Evan On Oct 16, 2007, at 9:06 PM, Scott Michel wrote: > Evan: > > What you requested was...
2020 Aug 07
2
Branches which return values in SelectionDAG
...2, i1} %MultipleReturns 1 br %Cond, body, exit exit: ... Then, I attempted to combine the intrinsic, extractions, and branch together in the SelectionDAG. What I found, however, is that this concept, which seems fine in the LLVM IR, is not fine in the DAG. Specifically, there is a CopyToReg in the DAG that occurs between the intrinsic and the branch that saves off %DecVal. I presume it's there because the value is leaving the DAG (to be copied from in the next iteration). With the branch node returning that value instead, it seems like there's no legal location in which to pla...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6 t9: i64 = xor t7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combining: t10: i64 = and t2, t9 Combining: t9: i64...