search for: frameindices

Displaying 17 results from an estimated 17 matches for "frameindices".

2009 Jan 15
2
[LLVMdev] Hitting assertion, unsure why
...ing this assertion: assert(I != VRBaseMap.end() && "Node emitted out of order - late"); I am not sure why this assertion is being triggered or what I changed that is causing it. This is asserting when SDValue is FrameIndexSDNode 1. I don't have any code that modified frameindices until my overloaded RegisterInfo function. I've attached the bc file. If I generate an unoptimized bc file then there is no issue, only when I turn optimizations on do I hit this problem. Thanks for any hints, Micah Villmow Systems Engineer Advanced Technology & Performance A...
2009 Jan 15
2
[LLVMdev] Hitting assertion, unsure why
...t(I != VRBaseMap.end() && "Node emitted out of order - late"); > > I am not sure why this assertion is being triggered or what I changed that > is causing it. > > This is asserting when SDValue is FrameIndexSDNode 1. > > I don't have any code that modified frameindices until my overloaded > RegisterInfo function. > > I've attached the bc file. If I generate an unoptimized bc file then there > is no issue, only when I turn optimizations on do I hit this problem. > I got this too. It's related to debug information being in flux right now. I b...
2009 Jan 15
0
[LLVMdev] Hitting assertion, unsure why
...t(I != VRBaseMap.end() && "Node emitted out of order - late"); > > I am not sure why this assertion is being triggered or what I changed that > is causing it. > > This is asserting when SDValue is FrameIndexSDNode 1. > > I don't have any code that modified frameindices until my overloaded > RegisterInfo function. > > I've attached the bc file. If I generate an unoptimized bc file then there > is no issue, only when I turn optimizations on do I hit this problem. > I got this too. It's related to debug information being in flux right now. I b...
2009 Jan 15
0
[LLVMdev] Hitting assertion, unsure why
..."Node emitted out of order - late"); >> >> I am not sure why this assertion is being triggered or what I changed > that >> is causing it. >> >> This is asserting when SDValue is FrameIndexSDNode 1. >> >> I don't have any code that modified frameindices until my overloaded >> RegisterInfo function. >> >> I've attached the bc file. If I generate an unoptimized bc file then > there >> is no issue, only when I turn optimizations on do I hit this problem. >> > I got this too. It's related to debug informatio...
2009 Jan 15
2
[LLVMdev] Hitting assertion, unsure why
..."Node emitted out of order - late"); >> >> I am not sure why this assertion is being triggered or what I changed > that >> is causing it. >> >> This is asserting when SDValue is FrameIndexSDNode 1. >> >> I don't have any code that modified frameindices until my overloaded >> RegisterInfo function. >> >> I've attached the bc file. If I generate an unoptimized bc file then > there >> is no issue, only when I turn optimizations on do I hit this problem. >> > I got this too. It's related to debug informatio...
2019 Feb 06
2
[RFC] arm64_32: upstreaming ILP32 support for AArch64
...o GitHub as https://github.com/TNorthover/llvm-project/tree/arm64_32-arch-pass, please excuse any artefacts of incompleteness). I feel like it's rapidly approaching an unpalatability horizon though. Most issues stem from the fact that not all pointers are visible or controllable in the IR: + FrameIndices: you can't change an alloca's address-space since it's fixed by the DataLayout. So they get through to the DAG as i32s, significantly complicating the Addressing-mode logic. + ConstantPool accesses are automatically put into addrspace(0) + BlockAddress is similar. + Some intrinsic...
2009 Jan 15
0
[LLVMdev] Hitting assertion, unsure why
...- late"); >>> >>> I am not sure why this assertion is being triggered or what I changed >> that >>> is causing it. >>> >>> This is asserting when SDValue is FrameIndexSDNode 1. >>> >>> I don't have any code that modified frameindices until my overloaded >>> RegisterInfo function. >>> >>> I've attached the bc file. If I generate an unoptimized bc file then >> there >>> is no issue, only when I turn optimizations on do I hit this problem. >>> >> I got this too. It's...
2009 Jan 27
3
[LLVMdev] Hitting assertion, unsure why
...- late"); >>> >>> I am not sure why this assertion is being triggered or what I changed >> that >>> is causing it. >>> >>> This is asserting when SDValue is FrameIndexSDNode 1. >>> >>> I don't have any code that modified frameindices until my overloaded >>> RegisterInfo function. >>> >>> I've attached the bc file. If I generate an unoptimized bc file then >> there >>> is no issue, only when I turn optimizations on do I hit this problem. >>> >> I got this too. It's...
2009 Jan 28
0
[LLVMdev] Hitting assertion, unsure why
...>>> I am not sure why this assertion is being triggered or what I > changed >>> that >>>> is causing it. >>>> >>>> This is asserting when SDValue is FrameIndexSDNode 1. >>>> >>>> I don't have any code that modified frameindices until my >>>> overloaded >>>> RegisterInfo function. >>>> >>>> I've attached the bc file. If I generate an unoptimized bc file >>>> then >>> there >>>> is no issue, only when I turn optimizations on do I hit th...
2009 Jan 30
1
[LLVMdev] Hitting assertion, unsure why
...>>> I am not sure why this assertion is being triggered or what I > changed >>> that >>>> is causing it. >>>> >>>> This is asserting when SDValue is FrameIndexSDNode 1. >>>> >>>> I don't have any code that modified frameindices until my >>>> overloaded >>>> RegisterInfo function. >>>> >>>> I've attached the bc file. If I generate an unoptimized bc file >>>> then >>> there >>>> is no issue, only when I turn optimizations on do I hit th...
2019 Feb 01
4
[EXT] [RFC] arm64_32: upstreaming ILP32 support for AArch64
Hi Eli, Thanks for the comments. On Thu, 31 Jan 2019 at 19:48, Eli Friedman <efriedma at quicinc.com> wrote: > > We teach CodeGenPrepare to sink GEPs as GEPs, and preserve the > > inbounds marker. This is the only way they can possibly be exposed to > > SDAG at the basic block level. > > Isn't addr-sink-using-gep already a thing? Yes, I'm not sure why I
2018 Jan 24
2
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...eGen/X86/variable-sized-darwin-bzero.ll > llvm/trunk/test/CodeGen/X86/vectorcall.ll > llvm/trunk/test/CodeGen/X86/x86-64-static-relo-movl.ll > llvm/trunk/test/CodeGen/X86/x86-repmov-copy-eflags.ll > llvm/trunk/test/CodeGen/XCore/memcpy.ll > llvm/trunk/test/DebugInfo/AArch64/frameindices.ll > llvm/trunk/test/DebugInfo/COFF/types-array.ll > llvm/trunk/test/DebugInfo/Generic/2010-10-01-crash.ll > llvm/trunk/test/DebugInfo/X86/array.ll > llvm/trunk/test/DebugInfo/X86/array2.ll > llvm/trunk/test/DebugInfo/X86/debug-ranges-offset.ll > llvm/trunk/test/DebugI...
2018 Jan 24
0
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
....ll llvm/trunk/test/CodeGen/X86/variable-sized-darwin-bzero.ll llvm/trunk/test/CodeGen/X86/vectorcall.ll llvm/trunk/test/CodeGen/X86/x86-64-static-relo-movl.ll llvm/trunk/test/CodeGen/X86/x86-repmov-copy-eflags.ll llvm/trunk/test/CodeGen/XCore/memcpy.ll llvm/trunk/test/DebugInfo/AArch64/frameindices.ll llvm/trunk/test/DebugInfo/COFF/types-array.ll llvm/trunk/test/DebugInfo/Generic/2010-10-01-crash.ll llvm/trunk/test/DebugInfo/X86/array.ll llvm/trunk/test/DebugInfo/X86/array2.ll llvm/trunk/test/DebugInfo/X86/debug-ranges-offset.ll llvm/trunk/test/DebugInfo/X86/pieces-2.ll llvm/tru...
2018 Jan 25
2
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...zed-darwin-bzero.ll >> llvm/trunk/test/CodeGen/X86/vectorcall.ll >> llvm/trunk/test/CodeGen/X86/x86-64-static-relo-movl.ll >> llvm/trunk/test/CodeGen/X86/x86-repmov-copy-eflags.ll >> llvm/trunk/test/CodeGen/XCore/memcpy.ll >> llvm/trunk/test/DebugInfo/AArch64/frameindices.ll >> llvm/trunk/test/DebugInfo/COFF/types-array.ll >> llvm/trunk/test/DebugInfo/Generic/2010-10-01-crash.ll >> llvm/trunk/test/DebugInfo/X86/array.ll >> llvm/trunk/test/DebugInfo/X86/array2.ll >> llvm/trunk/test/DebugInfo/X86/debug-ranges-offset.ll >>...
2018 Jan 25
3
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...>>> llvm/trunk/test/CodeGen/X86/vectorcall.ll >>> llvm/trunk/test/CodeGen/X86/x86-64-static-relo-movl.ll >>> llvm/trunk/test/CodeGen/X86/x86-repmov-copy-eflags.ll >>> llvm/trunk/test/CodeGen/XCore/memcpy.ll >>> llvm/trunk/test/DebugInfo/AArch64/frameindices.ll >>> llvm/trunk/test/DebugInfo/COFF/types-array.ll >>> llvm/trunk/test/DebugInfo/Generic/2010-10-01-crash.ll >>> llvm/trunk/test/DebugInfo/X86/array.ll >>> llvm/trunk/test/DebugInfo/X86/array2.ll >>> llvm/trunk/test/DebugInfo/X86/debug-ranges...
2018 Jan 25
0
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
....ll llvm/trunk/test/CodeGen/X86/variable-sized-darwin-bzero.ll llvm/trunk/test/CodeGen/X86/vectorcall.ll llvm/trunk/test/CodeGen/X86/x86-64-static-relo-movl.ll llvm/trunk/test/CodeGen/X86/x86-repmov-copy-eflags.ll llvm/trunk/test/CodeGen/XCore/memcpy.ll llvm/trunk/test/DebugInfo/AArch64/frameindices.ll llvm/trunk/test/DebugInfo/COFF/types-array.ll llvm/trunk/test/DebugInfo/Generic/2010-10-01-crash.ll llvm/trunk/test/DebugInfo/X86/array.ll llvm/trunk/test/DebugInfo/X86/array2.ll llvm/trunk/test/DebugInfo/X86/debug-ranges-offset.ll llvm/trunk/test/DebugInfo/X86/pieces-2.ll llvm/tru...
2018 Jan 25
0
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
....ll llvm/trunk/test/CodeGen/X86/variable-sized-darwin-bzero.ll llvm/trunk/test/CodeGen/X86/vectorcall.ll llvm/trunk/test/CodeGen/X86/x86-64-static-relo-movl.ll llvm/trunk/test/CodeGen/X86/x86-repmov-copy-eflags.ll llvm/trunk/test/CodeGen/XCore/memcpy.ll llvm/trunk/test/DebugInfo/AArch64/frameindices.ll llvm/trunk/test/DebugInfo/COFF/types-array.ll llvm/trunk/test/DebugInfo/Generic/2010-10-01-crash.ll llvm/trunk/test/DebugInfo/X86/array.ll llvm/trunk/test/DebugInfo/X86/array2.ll llvm/trunk/test/DebugInfo/X86/debug-ranges-offset.ll llvm/trunk/test/DebugInfo/X86/pieces-2.ll llvm/tru...