search for: frameindex

...pose any issue? Thanks again for your time! Jeff jeff at ubuntu:~/code$ llc -debug-only=isel dft_gf_msp.ll === main Initial selection DAG: BB#0 'main:entry' SelectionDAG has 18 nodes: t0: ch = EntryToken t4: ch = store<ST4[%retval]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32 t7: ch = store<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>, undef:i32 t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>, FrameIndex:i32<3>, undef:i32 t12: ch = store<ST4[%m]> t10, Constant:i32<0...

Suppose I have a target that does not have register+constant addressing mode. Then, I have DAG like: (store ..., (frameindex)) Targets like SPARC have the following patterns to catch this: def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; def STri : F3_2<3, 0b000100, (outs), (ins MEMri:$addr, IntRegs:$src), "st $src, [$addr]",...

...me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help me! Jeff jeff at ubuntu:~/code$ llc dft_gf_msp.ll LLVM ERROR: Cannot select: t28: ch = store<ST2[%le](align=4), trunc to i16> t27, t26, FrameIndex:i32<14>, undef:i32 t26: i32,ch = load<LD2[%sz](align=4), anyext from i16> t25, FrameIndex:i32<2>, undef:i32 t7: i32 = FrameIndex<2> t4: i32 = undef t17: i32 = FrameIndex<14> t4: i32 = undef In function: main LLVMTargetMachine(T, "e-m:e-p:32:32-i8:8...

On Dec 3, 2007, at 12:53 PM, Vladimir Prus wrote: > > Suppose I have a target that does not have register+constant > addressing mode. Then, I have DAG like: > > (store ..., (frameindex)) > > Targets like SPARC have the following patterns to catch this: > > def ADDRri : ComplexPattern<i32, 2, > "SelectADDRri", [frameindex], []>; > def STri : F3_2<3, 0b000100, > (outs), (ins MEMri:$addr, IntRegs:$src), >...

Evan Cheng wrote: > > On Dec 3, 2007, at 12:53 PM, Vladimir Prus wrote: > >> >> Suppose I have a target that does not have register+constant >> addressing mode. Then, I have DAG like: >> >> (store ..., (frameindex)) >> >> Targets like SPARC have the following patterns to catch this: >> >> def ADDRri : ComplexPattern<i32, 2, >> "SelectADDRri", [frameindex], []>; >> def STri : F3_2<3, 0b000100, >> (outs), (ins MEMri:$addr, IntRegs:$s...

Hi All I'm having nightmares with FrameIndexes during my backend development :( I have ComplexPatterns defined for my two addressing modes (RR and RI). Most of the time, FrameIndex operands appear to be on load/store nodes, in which case everything works fine as my custom addressing modes matchers work fine. Unfortunately, I now have an add...

...n 2019 at 06:26, Gleb Popov via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > >> While the store is being selected LLVM will just treat the value being > >> stored as a generic pointer-width integer unless you have written a > >> specific pattern for storing a FrameIndex somewhere. > > > > Actually, this is exactly my case. I have a pattern that looks like > > > > (store_stack IntRegs:$reg, FIOperand:$i) > > > > It worked for me when first operand was a register and now I stumbled > upon two FrameIndicies. > > That looks...

...t; def StoreStackF : InstRI<2, (outs), (ins IntRegs:$reg, i32imm:$i), > > "storestackf $reg, [$i]", [(store_stack i32:$reg, > AddrFI:$i)]>; > > > > I'm puzzled why despite having "IntRegs:$reg" in ins list, it still > matches FrameIndex: > > A register-class will match anything with the appropriate type (i32 > here). The idea is that any value of that type can be put into a > register somehow, and matching whatever it happens to be (a FrameIndex > in this case) is exactly what's needed to do that. > That'...

Hi all, I've been working on a backend of our architecture and noticed llvm performs following combining although one of operands is FrameIndex. Combining: t114: i64 = add FrameIndex:i64<0>, Constant:i64<56> Creating new node: t121: i64 = or FrameIndex:i64<0>, Constant:i64<56> ... into: t121: i64 = or FrameIndex:i64<0>, Constant:i64<56> This caused problem if frame pointer points 0x6000003...

...the operand being stored would be > first loaded into a register, and that register would be used instead? > > While the store is being selected LLVM will just treat the value being > stored as a generic pointer-width integer unless you have written a > specific pattern for storing a FrameIndex somewhere. Actually, this is exactly my case. I have a pattern that looks like (store_stack IntRegs:$reg, FIOperand:$i) It worked for me when first operand was a register and now I stumbled upon two FrameIndicies. That's probably > what you want so no need to change anything. > >...

...(outs ), [], "movsuto_a\t$ImmA,$RegB", [(store i32:$ImmA, i16:$RegB)],NoItinerary> { The selection DAG seems to be correct, but a FrameIndex of 0 as been introduced : Optimized legalized selection DAG: BB#0 'storeloadi32:' SelectionDAG has 6 nodes: t0: ch = EntryToken t5: ch = store<Volatile ST4[%ptr]> t0, Constant:i32<12>, FrameIndex:i16<0>, undef:i16 t6: ch = CLPISD::RET_FLAG t5 ISEL: Starting p...

Hello. After "Initial selection DAG" stage I get a DAG with node t14: ch = store<(store 4 into %ir.p45, align 8, addrspace 1)> t10, FrameIndex:i32<2>, FrameIndex:i32<3>, undef:i32 1. Where does it come from? Can I do anything to make it not appear? 2. If not, how do I change it so that the operand being stored would be first loaded into a register, and that register would be used instead? Like ch = StoreStackF<Mem:(store...

...a type of memory that can only be addressed via immediates. >> >> I've got this mostly working. However, I came across a problem which I've been unable to work around: lowering the IR (even without any optimisations enabled) often requires the pattern: >> >> i32 = FrameIndex <n> >> >> It isn't appropriate to do this with the proposed stack memory - it doesn't make sense to move the address into a register, as it isn't possible to move that back to the domain of an immediate. So I conditionally disabled this instruction. But that leads to...

Hi Mark, >> Sounds like your load / store address selection routine isn't working >> like what you expected. >> > > Thanks for the reply. Unfortunately, this doesn't seem to be the problem. do you handle truncating stores and extending loads? Ciao, Duncan.

Hey all, I am trying to implement a subtarget for the X86 architecture that only has 64 bit Registers. While running LLC on the IR for a very simple program, llc fails on an assertion that says it doesn't know how to promote ISD::FRAMEINDEX. I've tried to look for why how to promote the frameindex which is stored in a i32 variable to an i64 variable but can't seem to find where this is done. Can anyone help me with this? Cheers, Amogh -- The Wheel of Time turns and Ages come and go, leaving memories that become legend. Le...

...ode corresponding to input pointer SDvalue frindex = Op.getoperand(3); … SDValue returnValue = DAG.getNode(myNode1, DL, VT….); SDValue dstValue = DAG.getNode(myNode2, DL, VT….); // to save the value to dst pointer, I think I need some call like SDValue dstOut = DAG.getStore(chain, DL, dstValue, FrameIndex, MachinePointerInfo(), false, false, 0); “ I have two questions here: (1) should I return some merges values( returnValue, DstValue) ? or only return returnValue is right? ( the dag dumped out looks better if I return the merged values) (2) How the FrameIndex should be computed? I use DAG.getF...

...32-bit integers or pointers during register allocation, I have to define J as 64-bit, although it's physically 32-bit. This is a rude and dirty trick. I define my TargetData as "e-p:64:64:64-i32:32:32-f32:32:32-n32". When storing a register to stack frame, 'store' node take a FrameIndex as an input node, where FrameIndex produces a 64-bit operand for 'store'. In legalization phase, llc comes into a problem saying: ExpandIntegerResult #0: 0xadb1888: i64 = FrameIndex<1> [ORD=2] [ID=0] Do not know how to expand the result of this operator! To sovle this pro...

...because in AMD64, arguments is passed by register at first, then pass by memory when run out of register (AMD64 ABI 3.5.7 rule 10). Why this problem happened? When calling va_start to set va_list, overflow_arg_area is not set correctly. To set the overflow_arg_area correctly, we need to get the FrameIndex correctly. Now, here comes the problem, llvm doesn't handle it correctly. It accounts for StackSize to compute the FrameIndex, and if the StackSize is not aligned, it will compute the wrong FrameIndex. As a result overflow_arg_area will not be set correctly. My Solution: 1. Record the Align if...

Hi there, I have a mem address pattern basically copied from Sparc: def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex],[]> It can match FrameIndex<0> but was unable to match FrameIndex<1>. What is the difference between the two? How to match FrameIndex<1>? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-...

...ementation for others architecture but I didn't found an API to explicitly remove a node and trigger overall chain update. Could someone point out an example of API for such node deletion during DAG Combination? Regards, Dominique T. t56: ch = store<Volatile ST8[%l2]> t54:1, t55, FrameIndex:i16<1>, undef:i16 t57: v2f32,ch = load<Volatile LD8[%l1]> t56, FrameIndex:i16<0>, undef:i16 t58: v2f32,ch = load<Volatile LD8[%l1]> t57:1, FrameIndex:i16<0>, undef:i16 t59: f32 = extract_vector_elt t58, Constant:i16<0>...