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Hi, Is it possible to add a spill code (a pair of store /load ) to the machinecode in a pass before the instruction emitter? If so, how can I calculate the address (offset to the sp) for the spill store/load instructions? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

...d, e; a = (b - c) + (d - e); generates addc:i8 (subc:i8(b,c), subc:i8(d,e)) Looks like we need to custom lower addc here. LegalizeOp needs modification to allow custom lowering of ADDC, etc.I will post a patch to do the same. Any suggestions on how do we custom lower such things? is using MFI::CreateFixedObject () to generate a FI and then using that FI to Store one REG operand to memory and then generate a Load from that FI is a good idea? sth like store (subc:i8(d, e), FI) addc:i8(subc:i8(b,c) - load (FI)) - Sanjiv

...t; > addc:i8 (subc:i8(b,c), subc:i8(d,e)) > > Looks like we need to custom lower addc here. LegalizeOp needs > modification to allow custom lowering of ADDC, etc.I will post a patch > to do the same. > > Any suggestions on how do we custom lower such things? > is using MFI::CreateFixedObject () to generate a FI and then using > that > FI to Store one REG operand to memory and then generate a Load from > that > FI is a good idea? That should work. I don't see an alternative. I don't think it's legal to re-associate the expression, right? Evan > > &...

Hello everybody, hi Evan, this patch changes the lowering of arguments for tail call optimized calls. Before arguments that could be overwritten by each other were explicitly lowered to a stack slot, not giving the register allocator a chance to optimize. Now a sequence of copyto/copyfrom virtual registers ensures that arguments are loaded in (virtual) registers before they are lowered to the

...rgument to a virtual register unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; if (ObjSize != 4) { llvm_unreachable("Memory argument is wrong size - not 32 bit!"); } // Create the frame index object for this incoming parameter... int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); // Create the SelectionDAG nodes corresponding to a load from this // parameter. SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointe...

...ially problematic because the code is either expecting a > VirtualRegister or a RegisterSDNode in this location. I've checked all Unfortunately, I don't think anyone can help you until you can track down what is creating the FrameIndex. Why not set a break point in MachineFrameInfo::CreateFixedObject and CreateStackObject? Evan > > locations where I use the DAG.getCopyToReg function and none of them > pass in a frameindex. I explcitily check that I have a register before > passing in the value to Register number to CopyToReg, so this leads me > to believe that it is being gener...

...n a single function, and make it easy to differentiate between outgoing parameters and other local variables? I see that in the LowerCall function in ISelLowering.cpp, there's this code (From the MIPS target): * // Create the frame index object for this incoming parameter LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, VA.getLocMemOffset(), true); SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());* This looks like what I might want to change, but I'm not sure what's the right thing to do. Here's what I tried to change it to: *...

...signed integer is needed > at those points. I'm not convinced that's the best solution, at least conceptually. SlotSize really is an unsigned quantity, and though it's unlikely we'd like 0x80000000 to be interpreted as positive, rather than negative if it ever does occur. Also, CreateFixedObject seems to take an int64_t I'd suggest: + ISelLowering line 2459: cast FPDiff to int64_t. + ISelLowering line 3327: cast SlotSize to int64_t. + FrameLowering: declare TailCallReturnAddrDelta as int64_t and subtract SlotSize? It would also be really good if you could convert your IR into a test-...

...llSlots) { // Nope, just spill it anywhere convenient. FrameIdx = FFI->CreateStackObject(RegInfo->getSpillSize(Reg)/8, RegInfo->getSpillAlignment(Reg)/8); } else { // Spill it to the stack where we must. FrameIdx = FFI->CreateFixedObject(RegInfo->getSpillSize(Reg)/8, FixedSlot->second); } What's the division by 8 for? Neither 'CreateStackObject' nor 'getSpillAlignment' documentation say what units the size is, but everywhere it's in bytes. In my specific c...

Ok, I've had time to track this down a little bit more and I seem to have found another case where it fails. This is occurring during Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem seems to be that somehow the CopyToReg part of the switch statement in ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is especially problematic because the code is either

Hello. Could you please help me solve the following LLC bug happening at instruction selection time: ISEL: Starting pattern match on root node: t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64 Initial Opcode index to 157 Skipped scope entry (due to false predicate) at index 162, continuing at 236 Match failed at

Dear LLVM developers, I am a developer of SML#, an ML-style functional programming language developed at Tohoku University. Currently we are intending to use LLVM as the backend of our SML# compiler in our upcoming release, and have rewritten our frontend and runtime so that they can cooperate with LLVM. LLVM works extremely fine with our SML# compiler. We are grateful to LLVM community for

...ially problematic because the code is either expecting a > VirtualRegister or a RegisterSDNode in this location. I've checked all Unfortunately, I don't think anyone can help you until you can track down what is creating the FrameIndex. Why not set a break point in MachineFrameInfo::CreateFixedObject and CreateStackObject? Evan > > locations where I use the DAG.getCopyToReg function and none of them > pass in a frameindex. I explcitily check that I have a register before > passing in the value to Register number to CopyToReg, so this leads me > to believe that it is being gener...