llvm dev - Sep 2013 - [LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?

Hi, LLVM,

I found LLVM codegen has 3 passes for instruction scheduling:

1) pre-ra sched
2) post-ra sched
3) mi sched.

for RISC machines, there are data hazard cases appear only after Register
Allocation(RA).  for example, $t0 is used immediately after writing(RAW):

ld $t0, MEM
add $t2, $t0, $0

There may be one or more stall in pipeline. Instruction scheduler can
detect this kinds of conflict and insert other instructions to avoid
pipeline bubble. I think this work only can be done after RA.  If so,
what's the purpose for 1). I found 1) is mandatory  and 2/3) are optional.
Further, at least one target enable pre-RA-sched with harzardRecognizer.
Does it really work out? you can resolve data hazard using pre-RA-sched
only?

thanks,
--lx
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20130919/f107f3cc/attachment.html>

Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you
will have to compile with -O3.

You can also invoke the MI (pre-RA) scheduler with llc option
"-enable-misched". As you have pointed out, the post-isel scheduler is
mandatory, and therefore you don't have to give any command line options.

Currently, mips has only one generic scheduling itinerary model in
MipsSchedule.td that is not tailored to any specific core, so you might
have to tweak it to have the scheduler generate efficient code for your
target.


On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com> wrote:
> Hi, LLVM,
>
> I found LLVM codegen has 3 passes for instruction scheduling:
>
> 1) pre-ra sched
> 2) post-ra sched
> 3) mi sched.
>
> for RISC machines, there are data hazard cases appear only after Register
> Allocation(RA).  for example, $t0 is used immediately after writing(RAW):
>
> ld $t0, MEM
> add $t2, $t0, $0
>
> There may be one or more stall in pipeline. Instruction scheduler can
> detect this kinds of conflict and insert other instructions to avoid
> pipeline bubble. I think this work only can be done after RA.  If so,
> what's the purpose for 1). I found 1) is mandatory  and 2/3) are
optional.
> Further, at least one target enable pre-RA-sched with harzardRecognizer.
> Does it really work out? you can resolve data hazard using pre-RA-sched
> only?
>
> thanks,
> --lx
>
>
>
>
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20130919/ed16ac1e/attachment.html>

Akira,

Thanks you for response.

I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But
I found mips codes are good enough by default. basically, I can not easily
eyeball any bubbles.
I don't understand how they can do that without post-RA-sched.
pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little
information and they can only schedule node in topology order. It assumes
any SU is one cycle delay.  I don't think pre-ra-sched consider any
pipeline details.

thanks,
--lx



On Fri, Sep 20, 2013 at 5:39 AM, Akira Hatanaka <ahatanak at gmail.com>
wrote:
> Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so
you
> will have to compile with -O3.
>
> You can also invoke the MI (pre-RA) scheduler with llc option
> "-enable-misched". As you have pointed out, the post-isel
scheduler is
> mandatory, and therefore you don't have to give any command line
options.
>
> Currently, mips has only one generic scheduling itinerary model in
> MipsSchedule.td that is not tailored to any specific core, so you might
> have to tweak it to have the scheduler generate efficient code for your
> target.
>
>
> On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com>
wrote:
>
>> Hi, LLVM,
>>
>> I found LLVM codegen has 3 passes for instruction scheduling:
>>
>> 1) pre-ra sched
>> 2) post-ra sched
>> 3) mi sched.
>>
>> for RISC machines, there are data hazard cases appear only after
Register
>> Allocation(RA).  for example, $t0 is used immediately after
writing(RAW):
>>
>> ld $t0, MEM
>> add $t2, $t0, $0
>>
>> There may be one or more stall in pipeline. Instruction scheduler can
>> detect this kinds of conflict and insert other instructions to avoid
>> pipeline bubble. I think this work only can be done after RA.  If so,
>> what's the purpose for 1). I found 1) is mandatory  and 2/3) are
optional.
>> Further, at least one target enable pre-RA-sched with
harzardRecognizer.
>> Does it really work out? you can resolve data hazard using pre-RA-sched
>> only?
>>
>> thanks,
>> --lx
>>
>>
>>
>>
>>
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20130920/c7e865e4/attachment.html>