Displaying 8 results from an estimated 8 matches for "mipsschedule".
2009 Aug 18
0
[LLVMdev] ARMSchedule.td MipsSchedule.td etc.
...anaged to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen.
--- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote:
> From: Carter Cheng <carter_cheng at yahoo.com>
> Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc.
> To: llvmdev at cs.uiuc.edu
> Date: Monday, August 17, 2009, 2:56 PM
> I apologize if this has been asked
> before but which classes utilize the information in these
> files? I am asking since I am trying to extend the MIPS
> backend to 64bit among other things.
>
&g...
2009 Aug 17
2
[LLVMdev] ARMSchedule.td MipsSchedule.td etc.
I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things.
Thanks in advance,
Carter.
2009 Aug 18
1
[LLVMdev] ARMSchedule.td MipsSchedule.td etc.
...r
> myself. I am guessing that this information is used by the Schedule*
> classes in CodeGen.
>
> --- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote:
>
>> From: Carter Cheng <carter_cheng at yahoo.com>
>> Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc.
>> To: llvmdev at cs.uiuc.edu
>> Date: Monday, August 17, 2009, 2:56 PM
>> I apologize if this has been asked
>> before but which classes utilize the information in these
>> files? I am asking since I am trying to extend the MIPS
>> backend to 64bit among...
2013 Sep 20
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, Akira,
I found you maintain mips MipsSchedule.td. does it correct? in
MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
ByPass info out there.
are you sure this reflects the real R4xxx/R5xxx processors.
why IILoad uses funcition unit ALU?
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
for...
2013 Sep 20
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
...invoke the MI (pre-RA) scheduler with llc option
> "-enable-misched". As you have pointed out, the post-isel scheduler is
> mandatory, and therefore you don't have to give any command line options.
>
> Currently, mips has only one generic scheduling itinerary model in
> MipsSchedule.td that is not tailored to any specific core, so you might
> have to tweak it to have the scheduler generate efficient code for your
> target.
>
>
> On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>
>> Hi, LLVM,
>>
>> I found LLVM c...
2013 Sep 25
1
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote:
> Hi, Akira,
>
> I found you maintain mips MipsSchedule.td. does it correct? in
> MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
> ByPass info out there.
> are you sure this reflects the real R4xxx/R5xxx processors.
>
> why IILoad uses funcition unit ALU?
> InstrItinData<IILoad , [InstrStag...
2013 Sep 19
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
...with -O3.
You can also invoke the MI (pre-RA) scheduler with llc option
"-enable-misched". As you have pointed out, the post-isel scheduler is
mandatory, and therefore you don't have to give any command line options.
Currently, mips has only one generic scheduling itinerary model in
MipsSchedule.td that is not tailored to any specific core, so you might
have to tweak it to have the scheduler generate efficient code for your
target.
On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com> wrote:
> Hi, LLVM,
>
> I found LLVM codegen has 3 passes for instruction sch...
2013 Sep 19
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, LLVM,
I found LLVM codegen has 3 passes for instruction scheduling:
1) pre-ra sched
2) post-ra sched
3) mi sched.
for RISC machines, there are data hazard cases appear only after Register
Allocation(RA). for example, $t0 is used immediately after writing(RAW):
ld $t0, MEM
add $t2, $t0, $0
There may be one or more stall in pipeline. Instruction scheduler can
detect this kinds of conflict