Displaying 4 results from an estimated 4 matches for "r4xxx".
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2013 Sep 20
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, Akira,
I found you maintain mips MipsSchedule.td. does it correct? in
MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
ByPass info out there.
are you sure this reflects the real R4xxx/R5xxx processors.
why IILoad uses funcition unit ALU?
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
for my previous question, I have new input after reading the code.
pre-RA-sched is derived from ScheduleDAGSNodes, but post-RA-sched and
mi-sched are both derived from Sc...
2013 Sep 20
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Akira,
Thanks you for response.
I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But
I found mips codes are good enough by default. basically, I can not easily
eyeball any bubbles.
I don't understand how they can do that without post-RA-sched.
pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little
information and they can only schedule node in topology
2002 Mar 08
0
[Bug 151] New: 3.0.2p1 and 3.1p1 fail to build.
...I have just recieved 7.3.1.3m from SGI, but cannot update compilers until I've
had a chance to announce to all developers that the change is coming, and when.
%cat /etc/compiler.defaults
-DEFAULT:abi=n32:isa=mips3:proc=r4k
The above to build the binaries 32bit, as I have Indigo R4000 and Indy R4xxx
machines I have to support as well.
%gcc -v
Reading specs from
/usr/local/gcc-2.95.1/lib/gcc-lib/mips-sgi-irix6.5/2.95.1/specs
gcc version 2.95.1 19990816 (release)
And now for the make output:
First with MIPSpro:
%gmake
(cd openbsd-compat && gmake)
gmake[1]: Entering directory
`/home/ja...
2013 Sep 25
1
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
...at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote:
> Hi, Akira,
>
> I found you maintain mips MipsSchedule.td. does it correct? in
> MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
> ByPass info out there.
> are you sure this reflects the real R4xxx/R5xxx processors.
>
> why IILoad uses funcition unit ALU?
> InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
>
>
This means IILoad instructions use resource ALU for three cycles. I don't
remember why only two functional units (ALU and IMULDIV) are defined a...