Displaying 3 results from an estimated 3 matches for "iiload".
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2013 Sep 20
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, Akira,
I found you maintain mips MipsSchedule.td. does it correct? in
MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
ByPass info out there.
are you sure this reflects the real R4xxx/R5xxx processors.
why IILoad uses funcition unit ALU?
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
for my previous question, I have new input after reading the code.
pre-RA-sched is derived from ScheduleDAGSNodes, but post-RA-sched and
mi-sched are both derived from ScheduleDAGInstrs.that means pre...
2013 Sep 20
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Akira,
Thanks you for response.
I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But
I found mips codes are good enough by default. basically, I can not easily
eyeball any bubbles.
I don't understand how they can do that without post-RA-sched.
pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little
information and they can only schedule node in topology
2013 Sep 25
1
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
...mail.com> wrote:
> Hi, Akira,
>
> I found you maintain mips MipsSchedule.td. does it correct? in
> MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
> ByPass info out there.
> are you sure this reflects the real R4xxx/R5xxx processors.
>
> why IILoad uses funcition unit ALU?
> InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
>
>
This means IILoad instructions use resource ALU for three cycles. I don't
remember why only two functional units (ALU and IMULDIV) are defined and
used in this .td file, but this woul...