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...ext part -------------- ;; 1st PassInfo (this=0x2aaaac3472a0, name=0x2aaaabe24421 "Target Data Layout", arg=0x2aaaabe24434 "targetdata", pi=17004736, normal=0xada74e <llvm::Pass* llvm::callDefaultCtor<llvm::TargetData>()>, isCFGOnly=false, is_analysis=true) at /home/xliu/dev/llvm/include/llvm/PassSupport.h:59 (gdb) bt #0 PassInfo (this=0x2aaaac3472a0, name=0x2aaaabe24421 "Target Data Layout", arg=0x2aaaabe24434 "targetdata", pi=17004736, normal=0xada74e <llvm::Pass* llvm::callDefaultCtor<llvm::TargetData>()>, isCFGOnly=false, is_ana...

...t; I believe you are correct. Fixed thusly: > > dzur:~/sources/llvm> git svn dcommit > Committing to https://llvm.org/svn/llvm-project/llvm/trunk ... > M lib/MC/MCAnalysis/MCObjectDisassembler.cpp > Committed r214416 > > -eric > > > On Thu, Jul 31, 2014 at 10:26 AM, xliu <navy.xliu at gmail.com> wrote: >> my compiler gave me a warning in MCObjectDisassembler.cpp. it found a >> self-comparation in loop condition. I think it's a typo. >> >> the suspicious code was introduced by this patch: >> >> From f176482752fbea3139394...

my compiler gave me a warning in MCObjectDisassembler.cpp. it found a self-comparation in loop condition. I think it's a typo. the suspicious code was introduced by this patch: >From f176482752fbea3139394e280adfb10270dd3aac Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha <ahmed.bougacha at gmail.com> Date: Wed, 21 Aug 2013 07:28:55 +0000 Subject: MC CFG: Support disassembly at

...Currently, mips has only one generic scheduling itinerary model in > MipsSchedule.td that is not tailored to any specific core, so you might > have to tweak it to have the scheduler generate efficient code for your > target. > > > On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com> wrote: > >> Hi, LLVM, >> >> I found LLVM codegen has 3 passes for instruction scheduling: >> >> 1) pre-ra sched >> 2) post-ra sched >> 3) mi sched. >> >> for RISC machines, there are data hazard cases appear only after Regist...

...Collection ... for my testcase, I found -enable-misched is helpful for ARM, they reduce stall numbers from 205 to 160. however, mips is adverse impact. the stall number increases from 554 to 560. this doesn't make any sense. thanks --lx On Fri, Sep 20, 2013 at 10:50 AM, Liu Xin <navy.xliu at gmail.com> wrote: > Akira, > > Thanks you for response. > > I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But > I found mips codes are good enough by default. basically, I can not easily > eyeball any bubbles. > I don't understand how they...

On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled > by default for all architectures(3.4svn). I also don't understand the > algorithm. Could you point to me m...

On Sep 25, 2013, at 11:03 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > > > On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > >> Hi, Andrew, >> >> Thank you for answering my question....

...ss and run it after the > scheduler passes, e.g. in the pre-emit stage. > > if (addPreEmitPass()) > printAndVerify("After PreEmit passes") > > Though if it's too hacky for you then fair enough. > > Amara > > On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote: > > Amara, > > > > first, thank you for answering. but I found expandPsuedo instructions > > actually happens before post-RA, like the following code showing: > > your approach is a little hacky, right? : ) > > > > // Expand pseudo...

...helps you. > > The idea of improving the inliner is also great, but you may find that > it's needed for cases other than this one if i'm right about the > instcombine. > > Thanks > Pete > > Sent from my iPhone > > On Jan 5, 2015, at 3:16 AM, Liu Xin <navy.xliu at gmail.com> wrote: > > Philip, > > I post here because I think AlwaysInliner should inline it. I want to > detect the indirect calls for Inliner, and I want to hear inputs. > > let me define indirect call first in my idea. In one single expression, > one function may be...

...e algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > > hi, LLVM, > > > > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. > I still don't understand how llvm detects data hazard in pre-RA-sched. > pre-RA-sched is based on SDNode and all operands are vregs. Even you can...

On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers...

On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Akira, > > I found you maintain mips MipsSchedule.td. does it correct? in > MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no > ByPass info out there. > are you sure this reflects the real R4xxx/R5xxx processors. > >...

...I meant was to write your own expansion pass and run it after the scheduler passes, e.g. in the pre-emit stage. > if (addPreEmitPass()) printAndVerify("After PreEmit passes") Though if it's too hacky for you then fair enough. Amara On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote: > Amara, > > first, thank you for answering. but I found expandPsuedo instructions > actually happens before post-RA, like the following code showing: > your approach is a little hacky, right? : ) > > // Expand pseudo instructions before second scheduli...

On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote: > hi, LLVM, > > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of...

hi, LLVM, I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to optimize processor pipeline? thanks, --lx

Amara, first, thank you for answering. but I found expandPsuedo instructions actually happens before post-RA, like the following code showing: your approach is a little hacky, right? : ) // Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); printAndVerify("After ExpandPostRAPseudos"); // Run pre-sched2 passes. if (addPreSched2())

...lp me ? Thank you very much. --Miao Ye System administrator Dept of Math & CS Loyola university Chicago abel# niscat group.org_dir | grep ntadmin ntadmin::510:administrator,root abel# pwd /profiles/98spr abel# drwxrwxr-x 15 wwu ntadmin 512 Jul 20 15:09 wwu.pds drwxrwxr-x 15 xliu ntadmin 512 Jul 20 13:35 xliu.pds drwxrwxr-x 15 xwei ntadmin 512 Jun 20 17:30 xwei.pds drwxrwxr-x 15 ywang6 ntadmin 512 Jul 20 12:33 ywang6.pds drwxrwxr-x 15 yxu4 ntadmin 512 Jan 29 1998 yxu4.pds drwxrwxr-x 15 zcao ntadmin 512 Aug 27 09:47 zcao.p...

...e any command line options. Currently, mips has only one generic scheduling itinerary model in MipsSchedule.td that is not tailored to any specific core, so you might have to tweak it to have the scheduler generate efficient code for your target. On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, LLVM, > > I found LLVM codegen has 3 passes for instruction scheduling: > > 1) pre-ra sched > 2) post-ra sched > 3) mi sched. > > for RISC machines, there are data hazard cases appear only after Register > Allocation(RA). for example, $t...

...s in codegen. Many compiler has codegen optimizer. A DSE is good enough. Which posted patch about TBAA? you have yet another solution except decompose-vectors? thanks, --lx On Fri, Oct 25, 2013 at 6:06 PM, Richard Sandiford < rsandifo at linux.vnet.ibm.com> wrote: > Liu Xin <navy.xliu at gmail.com> writes: > > Hi, LLVM community, > > > > I write some code in hand using LLVM IR. for simplicity, I write them in > <4 > > x float>. now I found some stores for elements are useless. > > > > for example, If I store {0.0, 1.0, 2.0, 3.0} to...

Liu Xin <navy.xliu at gmail.com> writes: > Hi, LLVM community, > > I write some code in hand using LLVM IR. for simplicity, I write them in <4 > x float>. now I found some stores for elements are useless. > > for example, If I store {0.0, 1.0, 2.0, 3.0} to a <4 x float> %a. maybe >...