search for: misch

I see that there are several options to influence instruction scheduling, but there doesn't seem to be a lot of information about what they do, for example: -misched-topdown -misched-bottomup The description in MachineScheduler.cpp says: "Force top-down list scheduling" and "Force bottom-up list scheduling" Which isn't too helpful - where might I want to use these? Under what conditions might they improve an instruction schedule? S...

...Sep 12, 2016 at 10:37 AM, Phil Tomson <phil.a.tomson at gmail.com <mailto:phil.a.tomson at gmail.com>> wrote: > I see that there are several options to influence instruction scheduling, but there doesn't seem to be a lot of information about what they do, for example: > > -misched-topdown -misched-bottomup > > The description in MachineScheduler.cpp says: > > "Force top-down list scheduling" and "Force bottom-up list scheduling" > > Which isn't too helpful - where might I want to use these? Under what conditions might they impro...

In order for our instruction itineraries to be considered by the instruction scheduler we seem to have to pass -enable-misched to llvm: clang -O3 -mllvm -enable-misched -c some.c ..... If -enable-misched isn't included there it doesn't seem to take our instruction itineraries into account. What's the best way to make '-enable-misched' the default? Phil -------------- next part -------------- An HT...

On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled > by default for all architectures(3.4svn). I also don't understand the > algorithm. Could you point to me more papers or text materials about your > approach? it seems that you want to balance register pressure and ILP in > misched. &...

...gt; On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > >> Hi, Andrew, >> >> Thank you for answering my question. >> >> What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. > > It has be...

Hi, Andrew, Thank you for answering my question. What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. On Tue, Sep 24, 201...

Hi all, I meet this problem when compiling the TREAM benchmark ( http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. so I rewrite a simple code as attached link (foo.c), and compiled with two different methods: *method A:* *$clang -O3 foo.c -static -S -o foo.s -mllvm -enable-misc...

On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. It has been used in...

I am observing poor instruction scheduling in my out-of-tree target. The problem is an over-constrained scheduling DAG. In particular, the DAG includes spurious output dependencies on physical, non-register-allocatable registers. MISched already includes code to avoid this problem. However that code relies on information clobbered by the earlier pass LiveVariables. I wonder whether this is a bug in the LiveVariables pass and would appreciate feedback. Let me expand with a small example, Suppose my target declares machine inst...

On Oct 14, 2013, at 3:27 AM, Zakk <zakk0610 at gmail.com> wrote: > Hi all, > I meet this problem when compiling the TREAM benchmark (http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched > > The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. A bug for this is welcome. Pretty soon, I’ll be verifying A9 performance and changing the default scheduler. When I do this, I’ll be using the new machine...

I'm trying to figure out if there is a way to figure out what processor resource is used by which instruction during scheduling. This is purely for debugging purposes. Since I'm somewhat new to LLVM it is a bit difficult for me to figure this out. Initial idea was to insert comments in the generated assembly which would tell me what what resource is used. MachineInstr has a uint8_t

...efine N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] = scalar*c[j]; } $clang -O3 foo.c -static -S -o foo.s -mllvm -unroll-count=4 -mcpu=cortex-a9 -fno-vectorize -fno-slp-vectorize --target=arm -mfloat-abi=hard -mllvm -enable-misched -mllvm -scheditins=false per-operand cost model : Scale: push {lr} movw r12, :lower16:c movw lr, :lower16:b movw r3, #9216 movt r12, :upper16:c mov r1, #0 vmov.f64 d16, #3.000000e+00 movt lr, :upper16:b movt r3, #244 .LBB0_1: add r0, r12, r1 add r2, lr, r1 *vldr...

...red to be correct. > > Undef yes, but what relies on isDead being accurate (before live interval computation)? I only remember Andy/Quentin making those conservative correctness claims about the kill flags but not the dead/undef flags. I am also pretty sure the RegisterPressure.cpp / -verify-misched fail on missing dead flags (although -verify-misched fails in several instances anyway at the moment...) On the other hand I just checked the MachineVerifier which indeed only checks for sonervatively correct dead flags as you say and I can't think of other places being problematic with miss...

...t information on any failures that may show up. > > To properly enable the new scheduler, this hook is implemented in X86Subtarget: > > bool enableMachineScheduler() const LLVM_OVERRIDE { return true; } > > The MachineScheduler pass itself can be enabled/disabled with -enable-misched=true/false. But most of the codegen changes result rather from moving to source-order SD scheduling and subsequent register coalescing decisions. This makes it extremely challenging to keep the unit tests functioning during the transition. So you'll see unit test churn when I flip the switch....

...; > > > 2013/10/15 Andrew Trick <atrick at apple.com> > > On Oct 14, 2013, at 3:27 AM, Zakk <zakk0610 at gmail.com> wrote: > >> Hi all, >> I meet this problem when compiling the TREAM benchmark (http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched >> >> The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. > > A bug for this is welcome. Pretty soon, I’ll be verifying A9 performance and changing the default scheduler. When I do this, I’ll be usi...

...be missing some detail… > > Any help is appreciated, > > Jonas Paulsson Jonas, I'm sorry I forgot to respond to this. Hopefully you figured out how to debug it. I'm not sure if you're using the MachineScheduler pass or PostRAScheduler. For MachineScheduler, use -view-misched-dags and -debug-only=misched. For PostRA: -debug-only=post-RA-sched. Modifying the DAG edges is tricky to get right. But removePred() and addPred() are the basic primitives... -Andy -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piperm...

...pass for x86 tonight to collect information on any failures that may show up. To properly enable the new scheduler, this hook is implemented in X86Subtarget: bool enableMachineScheduler() const LLVM_OVERRIDE { return true; } The MachineScheduler pass itself can be enabled/disabled with -enable-misched=true/false. But most of the codegen changes result rather from moving to source-order SD scheduling and subsequent register coalescing decisions. This makes it extremely challenging to keep the unit tests functioning during the transition. So you'll see unit test churn when I flip the switch....

Hi, I am trying to add Hazard scheduling nodes after buildSchedGraph(), with a scheduler derived from ScheduleDAGInstrs. I get weird errors, so I wonder what I am doing wrong? What I am doing right now is: I have a created MI with opcode HAZARD that does not have parent, and I greate a SUnit(HazardMI). I use this one HazardMI for all hazard nodes. I remove all edges using removePred. I insert

...this approach? I must be missing some detail... Any help is appreciated, Jonas Paulsson Jonas, I'm sorry I forgot to respond to this. Hopefully you figured out how to debug it. I'm not sure if you're using the MachineScheduler pass or PostRAScheduler. For MachineScheduler, use -view-misched-dags and -debug-only=misched. For PostRA: -debug-only=post-RA-sched. Modifying the DAG edges is tricky to get right. But removePred() and addPred() are the basic primitives... -Andy -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piperm...

...mation on any failures that may show up. > > To properly enable the new scheduler, this hook is implemented in > X86Subtarget: > > bool enableMachineScheduler() const LLVM_OVERRIDE { return true; } > > The MachineScheduler pass itself can be enabled/disabled with > -enable-misched=true/false. But most of the codegen changes result rather > from moving to source-order SD scheduling and subsequent register > coalescing decisions. This makes it extremely challenging to keep the unit > tests functioning during the transition. So you'll see unit test churn when &gt...