Displaying 20 results from an estimated 37 matches for "instrstage".
2011 Oct 22
0
[LLVMdev] Instruction Scheduling Itineraries
...The itinerary has two lists, a list of pipeline stages and a list of
operand latencies. The latency of an instruction is captured by the
latency of its "definition" operands, so latency does not need to be
modeled in the pipeline stages at all.
A 2 wide, 1 deep pipeline (2x1) would be:
[InstrStage<1, [Pipe0, Pipe1]>]
A 2 wide, 4 deep pipeline (2x4) would be:
[InstrStage<1, [Pipe0, Pipe1]>]
Surprise. There is no difference in the pipeline description, because
the units are fully pipelined and we don't need to express latency
here. (I'm only showing the pipeline stages h...
2011 Dec 14
0
[LLVMdev] Help with hazards
...;)> [ORD=55]
[ID=25]
in other words, it produces a set of load, add, store triples,
non-interleaved, in order. The problem is that the result of the load is
not immediately available, and either is the result of the add. The
loads are covered by the itinerary:
InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>,
InstrStage<1, [AGEN]>,...
2016 Jun 06
2
Instruction Itineraries: question about operand latencies
...mory locations take a long time to
complete (on the order of 150 clock cycles). Since we don't have a way to
tell at compile time if the address being loaded from lies in slow or fast
memory, I've gone ahead and made all of the load numbers high, such as:
InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>,
However, I see that there is another field which I haven't specified where
operand latencies are specified. Here's an example from
ARMScheduleA8.td:
InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
Now I'm wondering if In...
2015 Dec 04
2
InstrStage, Interpretation of getUnits()
Here is the code
<https://github.com/llvm-mirror/llvm/blob/c68dcdb413079d92118839dbd835e125293f411a/include/llvm/MC/MCInstrItineraries.h#L75>
for InstrStage::getUnits()
/// \brief Returns the choice of FUs.
unsigned getUnits() const { return Units_; }
This method returns an integer. How does one interpret it? As far as I see
it it should tell me what resources are used by a given stage but I can't
figure out what a return value means. Would anyon...
2013 Feb 11
2
[LLVMdev] DFAPacketizer
...mdev at cs.uiuc.edu
*Subject:* [LLVMdev] DFAPacketizer
Hi,
I am having problems writing the ProcessorItineraries list. As
instructions on my VLIW target have varying size I want to model both
cpu units and bundle bits as FUs. The following does not work, to my
surprise:
InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,
InstrStage<1, [ALU1, ALU2]>]>
I want to express that there are two ALU's, and four bundle slots, and
in this case while allocating this type of instructions several times, I
would like to be allowed only two such instructions per cycle.
Re...
2016 Jun 08
2
Instruction Itineraries: question about operand latencies
...complete (on the order of 150 clock cycles). Since we don't have a way
>> to tell at compile time if the address being loaded from lies in slow or
>> fast memory, I've gone ahead and made all of the load numbers high, such as:
>>
>> InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>,
>>
>> However, I see that there is another field which I haven't specified
>> where operand latencies are specified. Here's an example from
>> ARMScheduleA8.td:
>>
>> InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_P...
2013 Feb 12
2
[LLVMdev] DFAPacketizer
...floating-point load
> simultaneously/
>
> /> uses units from a floating-point pipeline and a load/store pipeline./
>
> /Look into ARM itineraries, they contain a decent amount of such
> examples./
>
> //
>
> [Head feb 2013:]
>
> InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
>
> InstrStage<1, [SW_ALU0, SW_ALU1]>],
>
> [1]>,
>
> ------------------------------------------------------------------------
>
> *From:*Anshuman Dasgupta [mailto:adasgupt at codeaurora.org]
&g...
2015 Nov 16
3
DFAPacketizer, Scheduling and LoadLatency
...izer and the scheduler know a given
instruction is a load.
Here is what I'm talking about
Let's assume my VLIW target is described as follows:
def MyTargetItineraries :
ProcessorItineraries<[Slot0, Slot1], [], [
..............................
InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,
InstrItinData<LD, [InstrStage<1, [Slot0, Slot1]>]>, // <-- This
itinerary class describes load instructions
InstrItinData<BR, [InstrStage<1, [Slot0]>]>
..............................
]>;
def MyTargetModel :...
2013 Feb 12
0
[LLVMdev] DFAPacketizer
...NextCycles = 0)?
Yep!
> Specifically, consider a case where a floating-point load simultaneously
> uses units from a floating-point pipeline and a load/store pipeline.
Look into ARM itineraries, they contain a decent amount of such examples.
[Head feb 2013:]
InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
________________________________
From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org]
Sent: Monday, February 11, 2013...
2013 Feb 18
0
[LLVMdev] DFAPacketizer
...NextCycles = 0)?
Yep!
> Specifically, consider a case where a floating-point load simultaneously
> uses units from a floating-point pipeline and a load/store pipeline.
Look into ARM itineraries, they contain a decent amount of such examples.
[Head feb 2013:]
InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
________________________________
From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org]
Sent: Monday, February 11, 2013...
2013 May 09
2
[LLVMdev] Scheduling with RAW hazards
I have an instruction that takes no operands, and produces two results,
in two consecutive cycles.
I tried both of the following to my Schedule.td file:
InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>,
InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1,
[FuncU]>], [1, 2]>,
From what I can see in examples, these say that the first operand is
ready the cycle after issue, and the second is ready 2 cycles after issue.
But when I is...
2013 Dec 20
1
[LLVMdev] extra one cycle of getOperandLatency
...instruction issue the values which correspond to specific operand indices
are defined or read.
I thought if an instruction reads the operands at the first cycle
and produces the result at the second cycle. InstrItinData should be written
in something like this,
InstrItinData<IIC_iALUr ,[InstrStage<1, [FU_x]>], [2, 1, 1]>
Therefore, for operand latency of iALUr output to iALUr input is latency
of "1". However, by the implementatoin of getOperandLatency, the latency
of such definition is latency of "2". That's not what I want.
After some digging around, I f...
2011 Oct 07
1
[LLVMdev] Multiple-Pipeline Itinerary
In the example provided:
// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
// InstrStage<1, [A9_AGU]>],
// [3, 1], [A9_LdBypass]>,
If there is an operand dependency, does the scheduler assume that the
instruction is held in A9_Pipe1 or in A9_AGU until the operand is ready?
Thanks a...
2015 Nov 12
2
Way to specify instruction latency in itinerary scheduling model
Does anybody know how to specify instruction latency in the itinerary
scheduling model? For some reason no matter what I do I get a latency of 1.
--
Rail
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151111/161bd6cb/attachment.html>
2013 May 09
0
[LLVMdev] Scheduling with RAW hazards
On May 9, 2013, at 4:02 AM, Fraser Cormack <fraser at codeplay.com> wrote:
> I have an instruction that takes no operands, and produces two results, in two consecutive cycles.
>
> I tried both of the following to my Schedule.td file:
>
> InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>,
> InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, [FuncU]>], [1, 2]>,
>
> From what I can see in examples, these say that the first operand is ready the cycle after issue, and the second is ready 2 cycles after issue.
Y...
2013 May 13
1
[LLVMdev] Scheduling with RAW hazards
...m
> <mailto:fraser at codeplay.com>> wrote:
>
>> I have an instruction that takes no operands, and produces two
>> results, in two consecutive cycles.
>>
>> I tried both of the following to my Schedule.td file:
>>
>> InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>,
>> InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1,
>> [FuncU]>], [1, 2]>,
>>
>> From what I can see in examples, these say that the first operand is
>> ready the cycle after issue, and the second is...
2015 Nov 17
2
DFAPacketizer, Scheduling and LoadLatency
...d = 1 {
class InstrLD .... {
}
}
But that didn't seem to work. When I looked at the debug output the latency
for the load instruction was set to 1.
However when I changed load itinerary description in the schedule to
def MyTargetItineraries :
..............
InstrItinData<LD, [InstrStage<2, [BranchSlot, NonBranchSlot], 1>]>,
..............
That seem to produce correct latency in the debug output.
Do you know what could be the problem? Am I missing something? To give you
a full disclosure, I'm using LLVM 3.5 and at the moment I can't switch to
the latest versi...
2016 Jan 06
2
DFAPacketizer, Scheduling and LoadLatency
...to work. When I looked at the debug output the
>> latency for the load instruction was set to 1.
>>
>> However when I changed load itinerary description in the schedule to
>>
>> def MyTargetItineraries :
>> ..............
>> InstrItinData<LD, [InstrStage<2, [BranchSlot, NonBranchSlot], 1>]>,
>> ..............
>>
>> That seem to produce correct latency in the debug output.
>>
>> Do you know what could be the problem? Am I missing something? To give
>> you a full disclosure, I'm using LLVM 3.5 and...
2013 Sep 20
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, Akira,
I found you maintain mips MipsSchedule.td. does it correct? in
MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
ByPass info out there.
are you sure this reflects the real R4xxx/R5xxx processors.
why IILoad uses funcition unit ALU?
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
for my previous question, I have new input after reading the code.
pre-RA-sched is derive...
2011 Aug 15
2
[LLVMdev] Question on instruction itineraries
...r one cycle)
First of all, is there a document that describes the instruction itinerary
model in some detail ?
For example looking at MBlaze target MBlaeSchedule.td I can see something
like
MblazeSchedule.td
...
def IIImul : InstrItinClass;
...
InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
has something similar.
In Mblaze case I can see the result being used the very next cycle
mul *r3*, r6, r5
addik r3,* r3*, 4
similarly for my target (instead of...