llvm dev - Sep 2020 - Simulation of load-store forwarding with MI scheduler on AArch64

Hi list,

Is it possible to simulate load to store forwarding on aarch64 with MI
scheduling model on AArch64?
For instance $x0 data latency in the example below should be 1 cycle

ldr $x0, [$x1]
str $x0, [$x2]

But it should be 4 cycles if we have another instruction:

ldr $x0, [$x1]
add $x0, $x0, 4

For ALU instructions it’s possible to use either ReadAdvance or
SchedReadAdvance, but I don’t see how
to do this with WriteLD or WriteST. Is there some workaround?
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> On Sep 14, 2020, at 9:40 AM, Evgeny Leviant via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> Hi list,
>  
> Is it possible to simulate load to store forwarding on aarch64 with MI
scheduling model on AArch64?
> For instance $x0 data latency in the example below should be 1 cycle
>  
> ldr $x0, [$x1]
> str $x0, [$x2]
>  
> But it should be 4 cycles if we have another instruction:
>  
> ldr $x0, [$x1]
> add $x0, $x0, 4
>  
> For ALU instructions it’s possible to use either ReadAdvance or
SchedReadAdvance, but I don’t see how
> to do this with WriteLD or WriteST. Is there some workaround?
The main purpose of ReadAdvance is pipeline forwarding.

I think you can just want a read resource in your subtarget like this:

  def ReadAdr : SchedReadAdvance<3, [WriteLD]>

Briefly glancing at the AArch64 target I see this for stores:

  Sched<[WriteST]>;

So it doesn't look like there's any existing name for the store’s
address operand. You could add a general ReadAdr SchedRead resource
in AArch64Schedule.td. Then you would need to change the ReadAdr line in your
subtarget to an override:

  def : ReadAdvance<ReadAdr, 3, [WriteLD]>

Or instead you can just add a rule in your subtarget listing the opcodes or
using a regex, and using the ReadAdr resource that you defined in the same file.

  def : InstRW<[WriteST, ReadAdr], (instregex
"ST(someregex)$")>;

Being careful about store-pair and vector stores.

Then you always want to debug your target’s llvm-tblgen command by adding a flag
-debug-only=subtarget-emitter

And even trace the schedule for some simple cases with
-debug-only=machine-scheduler

I haven't actually done any of this in several years, someone with more
recent experience may have better tips.

-Andy
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Thanks for prompt response, Andy

This will work for cases when address is not modified. However this doesn’t seem
to work for pre/post increment load stores.
Consider data to address forwarding:

$x0 = ldr x0, [x1]
$x0, $x2 = ldr x2, [x0, 16]!

The second instruction will have it’s own latency for address modification ($x0
register). So I don’t see how we can use ReadAdr stuff
here. May be forwarding is not supposed to work in such cases for ARM cpus?
Cortex-A55 software optimization guide says this:

“load data from a limited set of load instructions can be forwarded from the
beginning of the wr pipeline stage to either the load or store AGU base operand”

However nothing is said about pre/post indexed forms.

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Sent: 15 сентября 2020 г. 7:04
To: Evgeny Leviant<mailto:eleviant at accesssoftek.com>
Cc: llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>
Subject: [EXTERNAL] Re: [llvm-dev] Simulation of load-store forwarding with MI
scheduler on AArch64

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On Sep 14, 2020, at 9:40 AM, Evgeny Leviant via llvm-dev <llvm-dev at
lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:

Hi list,

Is it possible to simulate load to store forwarding on aarch64 with MI
scheduling model on AArch64?
For instance $x0 data latency in the example below should be 1 cycle

ldr $x0, [$x1]
str $x0, [$x2]

But it should be 4 cycles if we have another instruction:

ldr $x0, [$x1]
add $x0, $x0, 4

For ALU instructions it’s possible to use either ReadAdvance or
SchedReadAdvance, but I don’t see how
to do this with WriteLD or WriteST. Is there some workaround?

The main purpose of ReadAdvance is pipeline forwarding.

I think you can just want a read resource in your subtarget like this:

  def ReadAdr : SchedReadAdvance<3, [WriteLD]>

Briefly glancing at the AArch64 target I see this for stores:

  Sched<[WriteST]>;

So it doesn't look like there's any existing name for the store’s
address operand. You could add a general ReadAdr SchedRead resource
in AArch64Schedule.td. Then you would need to change the ReadAdr line in your
subtarget to an override:

  def : ReadAdvance<ReadAdr, 3, [WriteLD]>

Or instead you can just add a rule in your subtarget listing the opcodes or
using a regex, and using the ReadAdr resource that you defined in the same file.

  def : InstRW<[WriteST, ReadAdr], (instregex
"ST(someregex)$")>;

Being careful about store-pair and vector stores.

Then you always want to debug your target’s llvm-tblgen command by adding a flag
-debug-only=subtarget-emitter

And even trace the schedule for some simple cases with
-debug-only=machine-scheduler

I haven't actually done any of this in several years, someone with more
recent experience may have better tips.

-Andy
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