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2020 Sep 15
2
[EXTERNAL] Re: Simulation of load-store forwarding with MI scheduler on AArch64
...ce $x0 data latency in the example below should be 1 cycle
ldr $x0, [$x1]
str $x0, [$x2]
But it should be 4 cycles if we have another instruction:
ldr $x0, [$x1]
add $x0, $x0, 4
For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how
to do this with WriteLD or WriteST. Is there some workaround?
The main purpose of ReadAdvance is pipeline forwarding.
I think you can just want a read resource in your subtarget like this:
def ReadAdr : SchedReadAdvance<3, [WriteLD]>
Briefly glancing at the AArch64 target I see this for stores:
Sched<[Wr...
2020 Sep 14
2
Simulation of load-store forwarding with MI scheduler on AArch64
...ce $x0 data latency in the example below should be 1 cycle
ldr $x0, [$x1]
str $x0, [$x2]
But it should be 4 cycles if we have another instruction:
ldr $x0, [$x1]
add $x0, $x0, 4
For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how
to do this with WriteLD or WriteST. Is there some workaround?
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