search for: readadv

Thanks Andrew. I have tried with recent tblgen, ReadAdvance would not work for multiple latencies. Maybe I should make improvement into tblgen if Pierre-Andre does not have the change anymore. However, I just a little curious about the situation I met. The hardware forwording may fail for different reasons, which different register read may have differ...

It does not work. I have tried to use the latest master today. But tblgen still give me information like error: Resources are defined for both SchedRead and its alias on processor MyArchModel def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>; ^ Unless I change "MyReadVector" to another read like "MyReadVector1", it would not work. Debugging into tblgen, there is no path to handle multiplle latencies for same Read... Anyway as you reminded, I am searching for more Targ...

Hi list, I happened to read below thread (written in 3 years ago). I think I may need this ReadAdvance feature to work with my ARCH. It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example: def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } ... def MyWri...

...9; field of 'MCWriteLatencyEntry' is for identifying the WriteResources of each defintion as commented on code. As you know, tablegen sets the 'WriteResourceID' field of 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is referenced by a 'ReadAdvance'. If we always set this field with 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses the 'WriteResourceID' field of 'MCWriteLatencyEntry' in 'computeOperandLatency' function. I think the pair of latency and write resource for defint...

...forwarding on aarch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how to do this with WriteLD or WriteST. Is there some workaround? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200914/e0820b42/attachment.html>

...want to do this if you have very complicated constraints. Can you provide an example of the most complicated instruction resources that you need to model? -Andy On Feb 19, 2014, at 4:57 AM, JinGu Kang <jingu at codeplay.com> wrote: > Hi Andy, > > I am sorry to misunderstand 'ReadAdvance' code. In order to support > resource per operand, I feel we need more table and function. If > possbile, I would like to listen to your opinion whether this feature is > useful or not. As I mentioned on previous e-mail, it will be useful to > access the latency and the resource...

...forwarding on aarch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how to do this with WriteLD or WriteST. Is there some workaround? The main purpose of ReadAdvance is pipeline forwarding. I think you can just want a read resource in your subtarget like this: def ReadAdr : SchedReadAdvance<3, [WriteLD]> Briefly...

...rce information of MI with 'getWriteProcResBegin()'. At this point, I would like to find the related resource information with each latency information. But TableGen generates the 'WriteResourceID' of 'MCWriteLatencyEntry' when the 'Write' is referenced by a 'ReadAdvance'. And the order of each information, which are resource and latency, is not same. Could you let me know whether it is possible to find the related resource information with each latency information or not? Thanks, JinGu Kang

...ovide an example of the most complicated instruction resources that you need to model? >> >> -Andy >> >> On Feb 19, 2014, at 4:57 AM, JinGu Kang <jingu at codeplay.com> wrote: >> >>> Hi Andy, >>> >>> I am sorry to misunderstand 'ReadAdvance' code. In order to support >>> resource per operand, I feel we need more table and function. If >>> possbile, I would like to listen to your opinion whether this feature is >>> useful or not. As I mentioned on previous e-mail, it will be useful to >>> acc...

...hat you need to model? >>>> >>>> -Andy >>>> >>>> On Feb 19, 2014, at 4:57 AM, JinGu Kang <jingu at codeplay.com> wrote: >>>> >>>>> Hi Andy, >>>>> >>>>> I am sorry to misunderstand 'ReadAdvance' code. In order to support >>>>> resource per operand, I feel we need more table and function. If >>>>> possbile, I would like to listen to your opinion whether this feature is >>>>> useful or not. As I mentioned on previous e-mail, it will be us...

...;>> -Andy >>>>>> >>>>>> On Feb 19, 2014, at 4:57 AM, JinGu Kang <jingu at codeplay.com> wrote: >>>>>> >>>>>>> Hi Andy, >>>>>>> >>>>>>> I am sorry to misunderstand 'ReadAdvance' code. In order to support >>>>>>> resource per operand, I feel we need more table and function. If >>>>>>> possbile, I would like to listen to your opinion whether this feature is >>>>>>> useful or not. As I mentioned on previo...

...The scheduler does not model those delays because they are irrelevant as long as they are consistent. Inaccuracies arise when instructions have different execution delays relative to each other, in addition to their intrinsic latency. To model those delays, the abstract model has various tools like ReadAdvance (bypassing) and the ability to extend the model with arbitrary "resources" and associate a cycle count with those resources for each instruction. (One tool currently missing is the ability to add a delay to ResourceCycles, but that would be easy to add). Now we come to out-of-order e...

Hi, I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. Are we modeling the decoder phase or the execution stage? Background: First of all, there seems to be different meanings of "issue" depending on which platform you're on: