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2020 Sep 14
2
Simulation of load-store forwarding with MI scheduler on AArch64
Hi list,
Is it possible to simulate load to store forwarding on aarch64 with MI scheduling model on AArch64?
For instance $x0 data latency in the example below should be 1 cycle
ldr $x0, [$x1]
str $x0, [$x2]
But it should be 4 cycles if we have another instruction:
ldr $x0, [$x1]
add $x0, $x0, 4
For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see
2020 Sep 15
2
[EXTERNAL] Re: Simulation of load-store forwarding with MI scheduler on AArch64
...n your subtarget to an override:
def : ReadAdvance<ReadAdr, 3, [WriteLD]>
Or instead you can just add a rule in your subtarget listing the opcodes or using a regex, and using the ReadAdr resource that you defined in the same file.
def : InstRW<[WriteST, ReadAdr], (instregex "ST(someregex)$")>;
Being careful about store-pair and vector stores.
Then you always want to debug your target’s llvm-tblgen command by adding a flag
-debug-only=subtarget-emitter
And even trace the schedule for some simple cases with -debug-only=machine-scheduler
I haven't actually done any of...