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...arch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how to do this with WriteLD or WriteST. Is there some workaround? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200914/e0820b42/attachment.html>

...arch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how to do this with WriteLD or WriteST. Is there some workaround? The main purpose of ReadAdvance is pipeline forwarding. I think you can just want a read resource in your subtarget like this: def ReadAdr : SchedReadAdvance<3, [WriteLD]> Briefly glancing at the AArc...

...ist for the same .Please correct me if am i wrong here. I was going through your reference @ https://llvm.org/svn/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td . But I couldn’t model some of the your definitions in the reference like a)Subtargets b)SchedReadWrite and SchedReadAdvance c) per-operand to the processor architecture instance . I will be glad if you give me some instance example on the above definitions Thanks in Advance ~Umesh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llv...

...was going through your reference @ > https://llvm.org/svn/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td > . > > > > But I couldn’t model some of the your definitions in the reference like > > > > a)Subtargets > > > > b)SchedReadWrite and SchedReadAdvance > > > > c) per-operand > > > > to the processor architecture instance . > > > > I will be glad if you give me some instance example on the above > definitions > > > > > > Thanks in Advance > > ~Umesh > -------------- next part...

...^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ But in line 479-483 of `AArch64SchedA57.td`, as shown below ``` def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; ``` In this code, an 1...

...t; . > > > > > > > > > > > > But I couldn?t model some of the your definitions in the reference > like > > > > > > > > > > > > a)Subtargets > > > > > > > > > > > > b)SchedReadWrite and SchedReadAdvance > > > > > > > > > > > > c) per-operand > > > > > > > > > > > > to the processor architecture instance . > > > > > > > > > > > > I will be glad if you give me some instance example on t...