search for: schedread

...arch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how to do this with WriteLD or WriteST. Is there some workaround? The main purpose of ReadAdvance is pipeline forwarding. I think you can just want a read resource in your subtarget like this: def ReadAdr : SchedReadAdvance<3, [WriteLD]> Briefly glancing at the A...

It does not work. I have tried to use the latest master today. But tblgen still give me information like error: Resources are defined for both SchedRead and its alias on processor MyArchModel def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>; ^ Unless I change "MyReadVector" to another read like "MyReadVector1", it would not work. Debugging into tblgen, there is no path to handle multiplle latencies for same Read......

...arch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how to do this with WriteLD or WriteST. Is there some workaround? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200914/e0820b42/attachment.html>

...I am working on a backend that uses the ProcResource scheduling model > and one limitation I found is that while it is possible to specify > multiple SchedWrites in a ReadAdvance record, each write uses the same > cycle count. I tried writing multiple ReadAdvance records for the same > SchedRead, but tablegen does not seem to allow that. > > It would be useful to have a per-write cycle count to model different > pipeline bypasses, where the cycle count depends on the (read, write) > pair and not just on the read. > > Two possible solutions are: 1) changing the 'Cycles...

...---------- Hi all, I am working on a backend that uses the ProcResource scheduling model and one limitation I found is that while it is possible to specify multiple SchedWrites in a ReadAdvance record, each write uses the same cycle count. I tried writing multiple ReadAdvance records for the same SchedRead, but tablegen does not seem to allow that. It would be useful to have a per-write cycle count to model different pipeline bypasses, where the cycle count depends on the (read, write) pair and not just on the read. Two possible solutions are: 1) changing the 'Cycles' field in (Proc)ReadAdv...

...’re target is interesting enough that you may be better off augmenting the standard machine model with your own model. Your scheduler plugin could keep your own tables or state machine to model the constraints. If you want to be clever, you could write tablegen code to build your model up from the SchedRead/Write definitions that are part of the standard model. You could add extra fields specific to your model. Were you previously using the old instruction itineraries, and now moving to the new model? -Andy > > Thanks for your kind response, > JinGu Kang > > On 2014-02-20 오전 2:27,...

...resting enough that you may be better off augmenting the standard machine model with your own model. Your scheduler plugin could keep your own tables or state machine to model the constraints. >> >> If you want to be clever, you could write tablegen code to build your model up from the SchedRead/Write definitions that are part of the standard model. You could add extra fields specific to your model. >> >> Were you previously using the old instruction itineraries, and now moving to the new model? >> >> -Andy >> >>> Thanks for your kind response, &gt...

...hat you may be better off augmenting the standard machine model with your own model. Your scheduler plugin could keep your own tables or state machine to model the constraints. >>>> >>>> If you want to be clever, you could write tablegen code to build your model up from the SchedRead/Write definitions that are part of the standard model. You could add extra fields specific to your model. >>>> >>>> Were you previously using the old instruction itineraries, and now moving to the new model? >>>> >>>> -Andy >>>> >&gt...

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.