Jie Zhou via llvm-dev
2019-Apr-14 18:17 UTC
[llvm-dev] [A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I would get adds r0, 4 rather than adds r8, 4. Similar problems happen to push and pop instructions. I can create a push/pop if the register list only contains registers R0 - R7, but for registers whose number are greater than R7, the generated asm code doesn’t have it. For example, BuildMI(……, TII->get(ARM::tPUSH), R8)….. would give me push {} Is this a bug in the LLVM ARM code generator? Or is there a reason why we cannot use big-number registers for add/sub and push/pop? Thanks, - Jie
Craig Topper via llvm-dev
2019-Apr-14 18:55 UTC
[llvm-dev] [A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7. tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument. ~Craig On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev < llvm-dev at lists.llvm.org> wrote:> Hi all, > > I’m trying to insert some add/sub and push/pop instructions in a > MachineFunction pass for ARMv7-M. However, I encountered something weird. > For an add, when I use > > BuildMI(….., TII->get(ARM::tADDi8), > reg).addReg(reg).addReg(reg).addImm(imm). > > if reg is R0 - R7, everything is fine: I would get something like > > adds r1, 4 > > But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the > correct register in the assembly code. For example, when I pass R8 to it, I > would get > > adds r0, 4 > > rather than > > adds r8, 4. > > Similar problems happen to push and pop instructions. I can create a > push/pop if the register list only contains registers R0 - R7, but > for registers whose number are greater than R7, the generated asm code > doesn’t have it. For example, > > BuildMI(……, TII->get(ARM::tPUSH), R8)….. > > would give me > > push {} > > Is this a bug in the LLVM ARM code generator? Or is there a reason why we > cannot use big-number registers for add/sub and push/pop? > > Thanks, > - Jie > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <lists.llvm.org/pipermail/llvm-dev/attachments/20190414/a770fe8e/attachment.html>
Jie Zhou via llvm-dev
2019-Apr-14 19:21 UTC
[llvm-dev] [A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2. It has 12 regular registers (R0 - R12), and R8 - R12 are used. I can generate mov instruction that from/ R8-R12 to/from R0-R6. From this ARM page infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot use them arbitrarily. The fact that we can use it to generate mov instructions but not add/sub and push/pop confuses me. - Jie On Apr 14, 2019, at 14:55, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7. tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument. ~Craig On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I would get adds r0, 4 rather than adds r8, 4. Similar problems happen to push and pop instructions. I can create a push/pop if the register list only contains registers R0 - R7, but for registers whose number are greater than R7, the generated asm code doesn’t have it. For example, BuildMI(……, TII->get(ARM::tPUSH), R8)….. would give me push {} Is this a bug in the LLVM ARM code generator? Or is there a reason why we cannot use big-number registers for add/sub and push/pop? Thanks, - Jie _______________________________________________ LLVM Developers mailing list llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org> lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev<urldefense.proofpoint.com/v2/url?u=https-3A__lists.llvm.org_cgi-2Dbin_mailman_listinfo_llvm-2Ddev&d=DwMFaQ&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=KAtyTEI8n3FritxDpKpR7rv3VjdmUs0luiVKZLb_bNI&m=U3D9KaSPCCtUPKPRKsCQl1uo2Kf6PSTT60lRuM6LGO8&s=VbLOmjk6zGsqyFH-PkHGWi4G9iNb4k60I8byBoTgJN4&e=> -------------- next part -------------- An HTML attachment was scrubbed... URL: <lists.llvm.org/pipermail/llvm-dev/attachments/20190414/ad7c898e/attachment.html>
Eli Friedman via llvm-dev
2019-Apr-15 18:57 UTC
[llvm-dev] [EXT] [A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
tADDi8 and tPUSH specifically refer to 16-bit instructions. Most 16-bit Thumb instructions are only allowed to refer to low registers. The corresponding 32-bit instructions are t2ADDri and t2STMDB_UPD. For more details on ARMv7-M instruction encodings, see the reference manual at developer.arm.com/docs/ddi0403/latest . You're getting weird behavior because the instruction encoder assumes the code doesn't contain any impossible instructions. -Eli> -----Original Message----- > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Jie Zhou via > llvm-dev > Sent: Sunday, April 14, 2019 11:18 AM > To: llvm-dev <llvm-dev at lists.llvm.org> > Subject: [EXT] [llvm-dev] [A bug?] Failed to use BuildMI to add R7 - R12 registers > for tADDi8 and tPUSH of ARM > > Hi all, > > I’m trying to insert some add/sub and push/pop instructions in a > MachineFunction pass for ARMv7-M. However, I encountered something weird. > For an add, when I use > > BuildMI(….., TII->get(ARM::tADDi8), > reg).addReg(reg).addReg(reg).addImm(imm). > > if reg is R0 - R7, everything is fine: I would get something like > > adds r1, 4 > > But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register > in the assembly code. For example, when I pass R8 to it, I would get > > adds r0, 4 > > rather than > > adds r8, 4. > > Similar problems happen to push and pop instructions. I can create a push/pop if > the register list only contains registers R0 - R7, but > for registers whose number are greater than R7, the generated asm code > doesn’t have it. For example, > > BuildMI(……, TII->get(ARM::tPUSH), R8)….. > > would give me > > push {} > > Is this a bug in the LLVM ARM code generator? Or is there a reason why we > cannot use big-number registers for add/sub and push/pop? > > Thanks, > - Jie > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
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