search for: addimm

...method can't be moved one step into class hierarchy, into ConstantIntegral::getRawValue The reason I'd like this is that to handle both ConstantInt and ConstantBool, I need the following: if (ConstantInt* CI = dyn_cast<ConstantInt>(V)) { BuildMI(*MBB, IPt, NM::MOVE, 1, Reg).addImm(CI->getRawValue()); } if (ConstantBool* CB = dyn_cast<ConstantBool>(V)) { BuildMI(*MBB, IPt, NM::MOVE, 1, Reg).addImm(CI->getalue()); } ... If getRawValue is moved to ConstantIntegral, I'd simply write if (ConstantIntegral* CI = dyn_cast<ConstantInt>(V)) {...

...cmp r0, r1 moveq r2, #1 To implement this, I first emit a compare instruction and then I'm trying to emit the conditional move, which is failing. BuildMI(&MBB, DL, TII->get(ARM::CMPrr)) .addReg(MI.getOperand(1).getReg()) .addReg(MI.getOperand(2).getReg()) .addImm(ARMCC::EQ); BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr), MI.getOperand(0).getReg()) .addImm(ARMCC::EQ) .addImm(1) .addReg(0); // 's' bit But with the last conditional move, I am a bit lost. The result of the condional move s...

...MFI.getObjectSize(MVT::i8), Align); BuildMI(MBB, MI, DL, get(Picoblaze::STORETOSTACK ));//.addMemOperand(MMO); if (RC == &Picoblaze::GR8RegClass) { // BuildMI(MBB, MI, DL, get(Picoblaze::ADD8ri )) // .addReg(Picoblaze::BP) // .addImm(FrameIdx); BuildMI(MBB, MI, DL, get(Picoblaze::STORE_I)) .addImm(FrameIdx) .addReg(SrcReg,getKillRegState(isKill)) ; // .addMemOperand(MMO); ;//addReg(Picoblaze::BP); // BuildMI(MBB, MI, DL, get(Picoblaze::ADD8ri )) // .addReg(Picoblaze::BP) // .addImm(-FrameIdx);...

..."prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code. The code for adding the 32-bit instruction is: BuildMI(MBB,MI,dl,TII->get(X86::PREFETCHNTA)).addReg(0).addImm(0).addReg(0).addImm(<constant>).addReg(0); The code above doesn't work for x86_64, so I think I need to change the operands to the instruction. However, I have no idea what the different register and immediate arguments to this instruction represent. Do they somehow encode the Mod/R...

...ing storeRegToStackSlot and loadFromStackSlot function for my Target. This Target can store/load one byte (not all word) from FrameIndex. If I need to store 16 bit register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(1) .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); After this store I catch assertion failed: "Instruction not found in maps", because only last of this ins...

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>> // Increment loop variable and jmp >> BuildMI(*MBB_erase, MBB_erase->end(), db, >> TII->get(X86::ADD64ri32),reg).addReg(reg).addImm(8); > > It looks like this instruction is defining virtual register "reg" the second time. Thx for your answer... Why would it define it again? I just want to use this register and add something to it... Cheers

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

...Buf = MI->getOperand(0).getReg(); + unsigned JmpLoc = MRI.createVirtualRegister(&SP::IntRegsRegClass); + + // Instruction to load jmp location + MIB = BuildMI(*MBB, MI, DL, TII->get(SP::LDri)) + .addReg(JmpLoc, RegState::Define) + .addReg(Buf) + .addImm(PtrSize); + MIB.setMemRefs(MMOBegin, MMOEnd); + + // TO DO: If we do 64-bit handling, this perhaps should be FLUSHW, not TA 3 + const long int TRAP_COND_ALWAYS = 0x08; + MIB = BuildMI(*MBB, MI, DL, TII->get(SP::TRAPri), SP::G0).addImm(3).addImm(TRAP_COND_ALWAYS); + + // Instruction to...

...I(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64rr)).addReg(regB).addReg(X86::RBP); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end); // mov dword[reg], 0x0 BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)).addReg(regB).addImm(1).addReg(0).addImm(0).addReg(0).addImm(0); BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), regC).addReg(regB).addImm(8); BuildMI(*MBB_cond, MBB_erase->end(), db, TII->get(X86::JMP_4)).addMBB(MBB_cond); // Erase intrinsic MI->eraseFromParent();...

...I found the following thread on the mailing list: http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html With your help and the information about the condition codes I was able to resolve the error:         BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1).add(predOps(ARMCC::AL); But how do I know how many and which condition codes each instruction needs? [MOVi takes 3 operands relating to the condition code (all after the immediate)] There is no info about that in the ARMInstrThumb.td file. -Julius On 03/23/2018 12:18 AM, Tom Stellard wrote:...

...    const MCInstrInfo *TII = TM.getMCInstrInfo();     DebugLoc DL;     BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock); these are working fine. When creating an compare instruction like cmp r0, 1 with:      BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1); I get the following error:     .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed. Which even after hours I can't make sense why the operand kind is wrong. Another thing I...

...eptember 11, 2012 1:42 PM To: Steve Checkoway Cc: LLVMdev at cs.uiuc.edu Subject: Re: [LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass ... > >> The code for adding the 32-bit instruction is: >> >> BuildMI(MBB,MI,dl,TII->get(X86::PREFETCHNTA)).addReg(0).addImm(0).add >> Reg(0).addImm(<constant>).addReg(0); > That's surprising to me. What are all of those registers and immediates for? That is precisely my question. What do all of those register and immediate arguments do? -- John T. The X86 backend records a machine memory operand u...

...0f 18 00 dd cc bb aa 00 00 00 00 (I probably got the mod r/m byte wrong, it's a /0 for prefetchnta at any rate). That's just going to add extra pressure to the icache. > The code for adding the 32-bit instruction is: > > BuildMI(MBB,MI,dl,TII->get(X86::PREFETCHNTA)).addReg(0).addImm(0).addReg(0).addImm(<constant>).addReg(0); That's surprising to me. What are all of those registers and immediates for? -- Stephen Checkoway

...gt; step into class hierarchy, into ConstantIntegral::getRawValue > > The reason I'd like this is that to handle both ConstantInt and ConstantBool, > I need the following: > > if (ConstantInt* CI = dyn_cast<ConstantInt>(V)) { > BuildMI(*MBB, IPt, NM::MOVE, 1, Reg).addImm(CI->getRawValue()); > } if (ConstantBool* CB = dyn_cast<ConstantBool>(V)) { > BuildMI(*MBB, IPt, NM::MOVE, 1, Reg).addImm(CI->getalue()); > } ... > > If getRawValue is moved to ConstantIntegral, I'd simply write > > if (ConstantIntegral* CI = dyn_c...

...egister inside the call to BuildMI, and inputs with "addReg(...)" and so on. All this actually does is fiddle the flags in an appropriate manner; you can emulate it with addReg, but why bother? So what you should be looking for is something like: BuildMI(LDri_ab).addReg(Dest).addReg(Src).addImm(Offset) and changing it to: BuildMI(LDri_ab, Dest).addReg(Src).addImm(Offset) Hope this helps. Tim.

...= TM.getMCInstrInfo(); > DebugLoc DL; > BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock); > > these are working fine. > When creating an compare instruction like cmp r0, 1 with: > > BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1); > > I get the following error: > > .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed. > According to ARMInstrThumb.td, tCMPi8's source arguments are reg, imm and...

...TII->get(X86::JE_4)).addMBB(MBB_end); // Update phi node BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::PHI), reg).addReg(reg).addMBB(MBB).addReg(reg).addMBB(MBB_erase); // Erase content of stack BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)) .addReg(reg).addImm(1).addReg(0).addImm(0).addReg(0) .addImm(0); // Increment loop variable and jmp BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), reg).addReg(reg).addImm(8); BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::JMP_4)).addMBB(MBB_cond); // Erase intrinsic MI->era...

...loadFromStackSlot function for my > Target. This Target can store/load one byte (not all word) from FrameIndex. > If I need to store 16 bit register I will must to split it to two > instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this store I catch assertion failed: "Instruction not found in > maps&quot...

...or prefetchnta at any rate). That's just going to add extra pressure to the icache. I think the instrumentation already adds a jump around the prefetchnta. > >> The code for adding the 32-bit instruction is: >> >> BuildMI(MBB,MI,dl,TII->get(X86::PREFETCHNTA)).addReg(0).addImm(0).addReg(0).addImm(<constant>).addReg(0); > That's surprising to me. What are all of those registers and immediates for? That is precisely my question. What do all of those register and immediate arguments do? -- John T. > >