Displaying 20 results from an estimated 171 matches for "addreg".
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2008 Jul 08
3
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...] in {
> + let Uses = [R0] in
> + def ATOMIC_LOAD_ADD_I32 : Pseudo<
>
> The "let Uses = [R0]" is not needed. The pseudo instruction will be
> expanded like this later:
>
> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
> + .addReg(ptrA).addReg(ptrB);
> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
> + .addReg(incr).addReg(dest);
> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
> + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
>
> The second instruction de...
2010 Sep 13
1
[LLVMdev] Multi-class register allocatable only in one class
...can only have some regs as
destination. I am not defining just one machine but let's say a "kind"
of similar machines, so I have separate cases, the number of regs that
can be destination of, for example, "add", can vary from just one to
several. They form the "AddRegs" class. Also, they are not spillable
to stack, but they can be copied to general purpose IntRegs.
Say I have two additions on my code, and just one reg in AddRegs. The
RA would run out of registers, so I change the ISel in a way the adds
are selected to my machineinstr going to AddRegs...
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...s = [R0] in
>> + def ATOMIC_LOAD_ADD_I32 : Pseudo<
>>
>> The "let Uses = [R0]" is not needed. The pseudo instruction will be
>> expanded like this later:
>>
>> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
>> + .addReg(ptrA).addReg(ptrB);
>> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
>> + .addReg(incr).addReg(dest);
>> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
>> + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
>>
>> Th...
2009 May 13
2
[LLVMdev] RFC: Code Gen Change!
...= 0x2,
Kill = 0x4,
Dead = 0x8,
EarlyClobber = 0x10,
ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill
};
}
class MachineInstrBuilder {
MachineInstr *MI;
public:
explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {}
/// addReg - Add a new virtual register operand...
///
const
MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
unsigned SubReg = 0) const {
MI->addOperand(MachineOperand::CreateReg(RegNo,
flags & RegS...
2008 Jul 04
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...chedInserter = 1 in {
+ let Uses = [CR0] in {
+ let Uses = [R0] in
+ def ATOMIC_LOAD_ADD_I32 : Pseudo<
The "let Uses = [R0]" is not needed. The pseudo instruction will be
expanded like this later:
+ BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+ .addReg(ptrA).addReg(ptrB);
+ BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
+ .addReg(incr).addReg(dest);
+ BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
The second instruction defines R0 and the 3rd reads R0...
2010 Sep 13
0
[LLVMdev] Multi-class register allocatable only in one class
On Sep 13, 2010, at 6:59 AM, Carlos Sánchez de La Lama wrote:
> Hi people,
>
> the LinearScan register allocator tries to use same register for both
> live intervals, if the new interval is defined by a register copy
> whose destination reg is compatible with the source register. This is
> ok. However, this "check for compatibility" is wrongly done IMHO.
>
2008 Jul 02
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...--> copy0MBB
- MachineBasicBlock *thisMBB = BB;
- MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
- MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
- unsigned SelectPred = MI->getOperand(4).getImm();
- BuildMI(BB, TII->get(PPC::BCC))
- .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
- MachineFunction *F = BB->getParent();
- F->getBasicBlockList().insert(It, copy0MBB);
- F->getBasicBlockList().insert(It, sinkMBB);
- // Update machine-CFG edges by transferring all successors of the current
- // block to the new block...
2009 May 13
0
[LLVMdev] RFC: Code Gen Change!
...t; enum {
> Define = 0x1,
> Implicit = 0x2,
> Kill = 0x4,
> Dead = 0x8,
> EarlyClobber = 0x10,
> ImplicitDefine = Implicit | Define,
> ImplicitKill = Implicit | Kill
> };
> }
[...]
> MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
> unsigned SubReg = 0) const {
Hi Bill,
I definitely like this change. The staccato bool arguments are
impossible to read. One comment:
If I forget to update an addReg(Reg, true) call, it will still compile
and work by accid...
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
...T == MVT::i32 && "Invalid Pointer Size!");
+
+ unsigned Buf = MI->getOperand(0).getReg();
+ unsigned JmpLoc = MRI.createVirtualRegister(&SP::IntRegsRegClass);
+
+ // Instruction to load jmp location
+ MIB = BuildMI(*MBB, MI, DL, TII->get(SP::LDri))
+ .addReg(JmpLoc, RegState::Define)
+ .addReg(Buf)
+ .addImm(PtrSize);
+ MIB.setMemRefs(MMOBegin, MMOEnd);
+
+ // TO DO: If we do 64-bit handling, this perhaps should be FLUSHW, not TA 3
+ const long int TRAP_COND_ALWAYS = 0x08;
+ MIB = BuildMI(*MBB, MI, DL, TII->get(SP::TR...
2014 Dec 08
2
[LLVMdev] Virtual register problem in X86 backend
...AddrRegClass = getRegClassFor(MVT::i64);
unsigned regA = MRI.createVirtualRegister(AddrRegClass);
unsigned regB = MRI.createVirtualRegister(AddrRegClass);
unsigned regC = MRI.createVirtualRegister(AddrRegClass);
// Set the indice
BuildMI(*MBB, MI, db,
TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP);
// Check condition
BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::PHI),
regB).addReg(regA).addMBB(MBB).addReg(regC).addMBB(MBB_erase);
BuildMI(*MBB_cond, MBB_cond->end(), db,
TII->get(X86::CMP64rr)).addReg(regB).addReg(X86::RBP);
BuildMI(*...
2010 Sep 13
2
[LLVMdev] Multi-class register allocatable only in one class
Hi people,
the LinearScan register allocator tries to use same register for both
live intervals, if the new interval is defined by a register copy
whose destination reg is compatible with the source register. This is
ok. However, this "check for compatibility" is wrongly done IMHO.
Say I have regclass1 with reg A, and regclass2 with regs {A, B}, but
regclass2 defines only
2008 Jul 08
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...ATOMIC_LOAD_ADD_I32 : Pseudo<
> >>
> >> The "let Uses = [R0]" is not needed. The pseudo instruction will be
> >> expanded like this later:
> >>
> >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
> >> + .addReg(ptrA).addReg(ptrB);
> >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
> >> + .addReg(incr).addReg(dest);
> >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
> >> + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);...
2012 Oct 24
0
[LLVMdev] Fwd: Debugging/Fixing 'Interval not live at use' errors
...ke:
That fits. This line
LDri_ab %FP, %SP, 4
should almost certainly be printed as:
%FP = LDri_ab %SP, 4
The most likely cause is a slightly malformed BuildMI that's adding
%FP without a define flag. Usually you put the destination register
inside the call to BuildMI, and inputs with "addReg(...)" and so on.
All this actually does is fiddle the flags in an appropriate manner;
you can emulate it with addReg, but why bother? So what you should be
looking for is something like:
BuildMI(LDri_ab).addReg(Dest).addReg(Src).addImm(Offset)
and changing it to:
BuildMI(LDri_ab, Dest).addR...
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...--> copy0MBB
- MachineBasicBlock *thisMBB = BB;
- MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
- MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
- unsigned SelectPred = MI->getOperand(4).getImm();
- BuildMI(BB, TII->get(PPC::BCC))
- .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
- MachineFunction *F = BB->getParent();
- F->getBasicBlockList().insert(It, copy0MBB);
- F->getBasicBlockList().insert(It, sinkMBB);
- // Update machine-CFG edges by transferring all successors of the current
- // block to the new block...
2016 Apr 15
3
[Sparc] Load address with SETHI
Hi,
I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc.
I imagine this is similar if I try to make a
2012 Oct 23
2
[LLVMdev] Debugging/Fixing 'Interval not live at use' errors
On Oct 23, 2012, at 2:10 AM, Stephen McGruer <stephen.mcgruer at gmail.com> wrote:
> I have a target backend which is currently causing live interval analysis to throw 'Interval not live at use' errors for many of my benchmarks. I imagine that this is caused by missing information for my target (probably in the instructioninfo tablegen?), but I am having difficulties in both
2014 Oct 28
2
[LLVMdev] Problem in X86 backend (again)
...;
MBB_cond->addSuccessor(MBB_erase);
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
unsigned reg = MRI.createVirtualRegister(AddrRegClass);
// Set the indice
BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(reg).addReg(X86::RSP);
// Create the for loop condition
BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64rr)).addReg(reg).addReg(X86::RBP);
BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end);
// Update phi node
BuildMI(*MBB_erase, MBB_erase->end(),...
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
PPCTargetLowering::EmitInstrWithCustomInserter has a reference
to the current MachineFunction for other purposes. Can you use
MachineFunction::getRegInfo instead?
Dan
On Jul 8, 2008, at 1:56 PM, Gary Benson wrote:
> Would it be acceptable to change MachineInstr::getRegInfo from private
> to public so I can use it from
> PPCTargetLowering::EmitInstrWithCustomInserter?
>
>
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...neFunction *F = BB->getParent();
- MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
- MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- unsigned SelectPred = MI->getOperand(4).getImm();
- BuildMI(BB, TII->get(PPC::BCC))
- .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
- F->insert(It, copy0MBB);
- F->insert(It, sinkMBB);
- // Update machine-CFG edges by transferring all successors of the current
- // block to the new block which will contain the Phi node for the select.
- sinkMBB->transferSuccessors(BB...
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary,
This does not patch cleanly for me (PPCISelLowering.cpp). Can you
prepare a updated patch?
Thanks,
Evan
On Jul 10, 2008, at 11:45 AM, Gary Benson wrote:
> Cool, that worked. New patch attached...
>
> Cheers,
> Gary
>
> Evan Cheng wrote:
>> Just cast both values to const TargetRegisterClass*.
>>
>> Evan
>>
>> On Jul 10, 2008, at 7:36