search for: buildmi

Hi Bill, I am using the following version of BuildMI : MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID, unsigned DestReg) I do the following : void createInstrs(std::vector<MachineInstr *>& ilist) { Machine Instr *mi; mi = Bu...

Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I w...

Hello everyone, I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. I started with branch instructions:     const TargetMachine &TM = MF.getTarget();     const MCInstrInfo *TII = TM.getMCInstrInfo();     DebugLoc DL;     BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock); these are working fine. When creating an compare instr...

...eryone, > > I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. > To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. > I started with branch instructions: > > const TargetMachine &TM = MF.getTarget(); > const MCInstrInfo *TII = TM.getMCInstrInfo(); > DebugLoc DL; > BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock); > > these are working...

...unsigned Align = MFI.getObjectAlignment(MVT::i8); MachineMemOperand *MMO = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MVT::i8), MachineMemOperand::MOStore, MFI.getObjectSize(MVT::i8), Align); BuildMI(MBB, MI, DL, get(Picoblaze::STORETOSTACK ));//.addMemOperand(MMO); if (RC == &Picoblaze::GR8RegClass) { // BuildMI(MBB, MI, DL, get(Picoblaze::ADD8ri )) // .addReg(Picoblaze::BP) // .addImm(FrameIdx); BuildMI(MBB, MI, DL, get(Picoblaze::STORE_I)) .addImm(FrameIdx)...

...but the command you suggest also doesn't work. After some research I found the following thread on the mailing list: http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html With your help and the information about the condition codes I was able to resolve the error:         BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1).add(predOps(ARMCC::AL); But how do I know how many and which condition codes each instruction needs? [MOVi takes 3 operands relating to the condition code (all after the immediate)] There is no info about that in the ARMIn...

Why do these two guys take a pointer to the basic block, whereas all other BuildMI functions take a reference? They are not checking for null or anything and I didn't see any potential declaration conflicts. Am I missing something? Is there a reason for this? inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL,...

...: Instr<... "LD32" ...>, Requires<[isV1]>; def LD32_v2 : Instr<... "LD.32" ...>, Requires<[isV2]>; This all works fine, but there is a large number of them which makes maintenance difficult. This also adds to the burden of selection when using 'BuildMI' in the C++ code, as I have to do things like: if (isV1()) BuildMI(..., TII->get(SHAVE::LD32_v1) else if (isV2()) BuildMI(..., TII->get(SHAVE::LD32_v2) What I would like, is for some mechanism that can substitute the version specific mnemonic dynamically (perhaps using a lo...

...e following assertion in leak detector. /llvm/lib/VMCore/LeakDetector.cpp:43: void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' failed. I am creating a list of instructions using BuildMI() and adding them to a basic block using BB->insert(). I am seeing this assertion after some number of insertions. Am I doing something wrong? Manjunath

...to:craig.topper at gmail.com>> wrote: I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7. tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument. ~Craig On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass f...

Dear All, I am working on a x86 backend machineFunction pass, where I am trying to save the hard coded address of an arbitrary machine basic block to memory in ASM. I know the assembly needed for this but am lost at how to construct the BuildMI(). Note that these machine basic blocks are not entry's to a function. but in the middle of the function. so using addGlobalAddress or addExternalSymbol are no use to me and am trying to avoid having to make a separate jump table section. Is a jump table section with symbols associated with th...

...nt: > > +let usesCustomDAGSchedInserter = 1 in { > + let Uses = [CR0] in { > + let Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > + .addReg(ptrA).addReg(ptrB); > + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > + .addReg(incr).addReg(dest); > + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > + .a...

Dear there, I'm trying to call BuildMI in my backend to add a machineinstr. BuildMI(MBB, I, I->getDebugLoc(), TII->get(Vanilla::MOV), Vanilla::R1).addReg(MI->getOperand(1).getReg()); But it gives me an error like this: 0 clang 0x000000010e61a56e llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 46 1 c...

...ector. > > /llvm/lib/VMCore/LeakDetector.cpp:43: > void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = > void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' > failed. > > I am creating a list of instructions using BuildMI() and adding them > to a basic block using BB->insert(). I am seeing this assertion after > some number of insertions. Am I doing something wrong? > Hi Manjunath, If you are using BuildMI(), you shouldn't have to re-insert the instruction into the machine basic block. -bw

...o match such behaviour automatically, I > actually only generate them manually for prologue/epilogue emission, so the > tablegen def is like: That fits. This line LDri_ab %FP, %SP, 4 should almost certainly be printed as: %FP = LDri_ab %SP, 4 The most likely cause is a slightly malformed BuildMI that's adding %FP without a define flag. Usually you put the destination register inside the call to BuildMI, and inputs with "addReg(...)" and so on. All this actually does is fiddle the flags in an appropriate manner; you can emulate it with addReg, but why bother? So what you shoul...

...sequentially executed? >> What level of codegen are you working at? There are various mechanisms that can be applied, depending on exactly what the constraints are that you need to preserve. >> >> —Owen > I have two machine instructions that I need to be together. > > BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) > .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); > BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) > .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); > > It's in Mips16ISelDagToDag.cpp >...

...>getRegInfo(); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); unsigned regA = MRI.createVirtualRegister(AddrRegClass); unsigned regB = MRI.createVirtualRegister(AddrRegClass); unsigned regC = MRI.createVirtualRegister(AddrRegClass); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); // Check condition BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::PHI), regB).addReg(regA).addMBB(MBB).addReg(regC).addMBB(MBB_erase); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64r...

...to:craig.topper at gmail.com>> wrote: I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7. tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument. ~Craig On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass f...

It looks like you are not using the right overloaded version of function BuildMI defined in MachineInstrBuilder.h. The register operand added to instruction sb should be a use, not a def operand. So this function should be called, BuildMI(BB, dl, TII->get(Mips::SB)).addReg(tmpReg1) instead of BuildMI(BB, dl, TII->get(Mips::SB), tmpReg1) On Sat, Jul 21, 2012 at 11:4...

...are you working at? There are various mechanisms > that can be applied, depending on exactly what the constraints are that you > need to preserve. > >>> > >>> -Owen > >> I have two machine instructions that I need to be together. > >> > >> BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) > >> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); > >> BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) > >> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); > >> > &g...