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Julius Hiller via llvm-dev

2018-Mar-22 16:29 UTC

[llvm-dev] ARM Backend BuildMI operand issues

Hello everyone,

I'm working on a MachineFunctionPass that inserts a list of instructions 
into an Module so a later Pass can work on them.
To do so I load a dummy .ll file created from a main stub, create the 
needed function stubs (ModulePass), insert Blocks and create 
instructions using BuildMI.
I started with branch instructions:

         const TargetMachine &TM = MF.getTarget();
         const MCInstrInfo *TII = TM.getMCInstrInfo();
         DebugLoc DL;
         BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock);

these are working fine.
When creating an compare instruction like cmp r0, 1 with:

          BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1);

I get the following error:

         .../include/llvm/MC/MCInst.h:81: int64_t
    llvm::MCOperand::getImm() const: Assertion `isImm() && "This is
not
    an immediate"' failed.

Which even after hours I can't make sense why the operand kind is wrong.

Another thing I noticed is that using ARM::tB results in the following 
error:

    .../include/llvm/ADT/SmallVector.h:154: const T&
    llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2>
     >::operator[](llvm::SmallVectorTemplateCommon<T,
    <template-parameter-1-2> >::size_type) const [with T    
llvm::MCOperand; <template-parameter-1-2> = void;
    llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2>
     >::const_reference = const llvm::MCOperand&;
    llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2>
     >::size_type = long unsigned int]: Assertion `idx < size()'
failed.

The architecture is ARMv6-m, I am using llvm 7, the dummy.ll was created 
with llvm 3.9
Hope to find some help here, best regards

Julius Hiller
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Tom Stellard via llvm-dev

2018-Mar-22 23:18 UTC

head link

[llvm-dev] ARM Backend BuildMI operand issues

On 03/22/2018 09:29 AM, Julius Hiller via llvm-dev
wrote:> Hello everyone,
> 
> I'm working on a MachineFunctionPass that inserts a list of
instructions into an Module so a later Pass can work on them.
> To do so I load a dummy .ll file created from a main stub, create the
needed function stubs (ModulePass), insert Blocks and create instructions using
BuildMI.
> I started with branch instructions:
> 
>         const TargetMachine &TM = MF.getTarget();
>         const MCInstrInfo *TII = TM.getMCInstrInfo();
>         DebugLoc DL;
>         BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock);
> 
> these are working fine.
> When creating an compare instruction like cmp r0, 1 with:
> 
>          BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1);
> 
> I get the following error:
> 
>         .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm()
const: Assertion `isImm() && "This is not an immediate"'
failed.
> 
According to ARMInstrThumb.td, tCMPi8's source arguments are reg, imm and
there is no explicit destination register, so what you want is:

BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1);

-Tom
> Which even after hours I can't make sense why the operand kind is
wrong.
>  
> Another thing I noticed is that using ARM::tB results in the following
error:
> 
>     .../include/llvm/ADT/SmallVector.h:154: const T&
llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2>
>::operator[](llvm::SmallVectorTemplateCommon<T,
<template-parameter-1-2> >::size_type) const [with T = llvm::MCOperand;
<template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T,
<template-parameter-1-2> >::const_reference = const
llvm::MCOperand&; llvm::SmallVectorTemplateCommon<T,
<template-parameter-1-2> >::size_type = long unsigned int]: Assertion
`idx < size()' failed.
> 
> The architecture is ARMv6-m, I am using llvm 7, the dummy.ll was created
with llvm 3.9
> Hope to find some help here, best regards
> 
> Julius Hiller
> 
> 
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

Julius Hiller via llvm-dev

2018-Mar-23 13:56 UTC

head link

[llvm-dev] ARM Backend BuildMI operand issues

Thank you for your help Tom

you are totally right with the registers but the command you suggest 
also doesn't work.
After some research I found the following thread on the mailing list: 
http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html
With your help and the information about the condition codes I was able 
to resolve the error:

             BuildMI(BB, BB.end(), DL,
    TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1).add(predOps(ARMCC::AL);

But how do I know how many and which condition codes each instruction 
needs? [MOVi takes 3 operands relating to the condition code (all after 
the immediate)]
There is no info about that in the ARMInstrThumb.td file.

-Julius

On 03/23/2018 12:18 AM, Tom Stellard wrote:> On 03/22/2018 09:29 AM, Julius Hiller via llvm-dev wrote:
>> Hello everyone,
>>
>> I'm working on a MachineFunctionPass that inserts a list of
instructions into an Module so a later Pass can work on them.
>> To do so I load a dummy .ll file created from a main stub, create the
needed function stubs (ModulePass), insert Blocks and create instructions using
BuildMI.
>> I started with branch instructions:
>>
>>          const TargetMachine &TM = MF.getTarget();
>>          const MCInstrInfo *TII = TM.getMCInstrInfo();
>>          DebugLoc DL;
>>          BuildMI(BB, BB.end(), DL,
TII->get(ARM::B)).addMBB(trgBlock);
>>
>> these are working fine.
>> When creating an compare instruction like cmp r0, 1 with:
>>
>>           BuildMI(BB, BB.end(), DL,
TII->get(ARM::tCMPi8),0).addImm(1);
>>
>> I get the following error:
>>
>>          .../include/llvm/MC/MCInst.h:81: int64_t
llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not
an immediate"' failed.
>>
> According to ARMInstrThumb.td, tCMPi8's source arguments are reg, imm
and
> there is no explicit destination register, so what you want is:
>
> BuildMI(BB, BB.end(), DL,
TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1);
>
> -Tom
>
>> Which even after hours I can't make sense why the operand kind is
wrong.
>>   
>> Another thing I noticed is that using ARM::tB results in the following
error:
>>
>>      .../include/llvm/ADT/SmallVector.h:154: const T&
llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2>
>::operator[](llvm::SmallVectorTemplateCommon<T,
<template-parameter-1-2> >::size_type) const [with T = llvm::MCOperand;
<template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T,
<template-parameter-1-2> >::const_reference = const
llvm::MCOperand&; llvm::SmallVectorTemplateCommon<T,
<template-parameter-1-2> >::size_type = long unsigned int]: Assertion
`idx < size()' failed.
>>
>> The architecture is ARMv6-m, I am using llvm 7, the dummy.ll was
created with llvm 3.9
>> Hope to find some help here, best regards
>>
>> Julius Hiller
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
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