Displaying 11 results from an estimated 11 matches for "tpush".
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2019 Apr 14
3
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
...4
rather than
adds r8, 4.
Similar problems happen to push and pop instructions. I can create a push/pop if the register list only contains registers R0 - R7, but
for registers whose number are greater than R7, the generated asm code doesn’t have it. For example,
BuildMI(……, TII->get(ARM::tPUSH), R8)…..
would give me
push {}
Is this a bug in the LLVM ARM code generator? Or is there a reason why we cannot use big-number registers for add/sub and push/pop?
Thanks,
- Jie
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
...e mov instructions but
not add/sub and push/pop confuses me.
- Jie
On Apr 14, 2019, at 14:55, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:
I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7.
tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument.
~Craig
On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <llvm-dev at lists.llvm.org&...
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
...e mov instructions but
not add/sub and push/pop confuses me.
- Jie
On Apr 14, 2019, at 14:55, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:
I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7.
tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument.
~Craig
On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <llvm-dev at lists.llvm.org&...
2015 Jan 11
3
[LLVMdev] [RFC] [PATCH] add tail call optimization to thumb1-only targets
...InCSI) {
+ // We need to restore LR and need a scratch register for this purpose
+ int StackSlotForSavedLR = CSI.size() - 1;
+ assert (StackSlotForSavedLR >= 0 && "Wrong Stack slot for LR.");
+
+ // Make sure that R4 may be used as scratch. Add an additional tPUSH (R4)
+ // if necessary.
+ if (!IsR4IncludedInCSI) {
+ IsR4ToBeAdditionallyAddedToPopIns = true;
+
+ AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPUSH))
+ .addReg(ARM::R4,RegState::Kill));
+
+ StackSlotForSavedLR ++;
+ }
+
+ AddDefaultPred(B...
2013 Sep 26
2
[LLVMdev] Register scavenger and SP/FP adjustments
...lign=4, at location [SP-1032]
fi#1: size=1024, align=4, at location [SP-2056]
fi#2: size=4, align=4, at location [SP-4]
fi#3: size=4, align=4, at location [SP-8]
Constant Pool:
cp#0: -2048, align=4
cp#1: 2048, align=4
BB#0: derived from LLVM BB %entry
Live Ins: %R4 %LR
tPUSH pred:14, pred:%noreg, %R4<kill>, %LR<kill>, %SP<imp-def>,
%SP<imp-use>; flags: FrameSetup
%vreg0<def> = tLDRpci <cp#0>, pred:14, pred:%noreg; flags:
FrameSetup tGPR:%vreg0
%SP<def,tied1> = tADDhirr %SP<tied0>, %vreg0<kill>, p...
2013 Sep 26
0
[LLVMdev] Register scavenger and SP/FP adjustments
...fi#1: size=1024, align=4, at location [SP-2056]
> fi#2: size=4, align=4, at location [SP-4]
> fi#3: size=4, align=4, at location [SP-8]
> Constant Pool:
> cp#0: -2048, align=4
> cp#1: 2048, align=4
>
> BB#0: derived from LLVM BB %entry
> Live Ins: %R4 %LR
> tPUSH pred:14, pred:%noreg, %R4<kill>, %LR<kill>, %SP<imp-def>, %SP<imp-use>; flags: FrameSetup
> %vreg0<def> = tLDRpci <cp#0>, pred:14, pred:%noreg; flags: FrameSetup tGPR:%vreg0
> %SP<def,tied1> = tADDhirr %SP<tied0>, %vreg0<kill>...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
...movss [edx], xmm3
+
+ pop edi
+ pop edx
+ pop ecx
+ pop ebx
+ pop eax
+ }
+#endif
+#if defined(GCC_COMPILER) && defined(_USE_SSE)
+ __asm__ __volatile__ (
+ "\tpush %%eax\n"
+ "\tpush %%edi\n"
+ "\tpush %%ecx\n"
+ "\txorps %%xmm3, %%xmm3\n"
+ "\txorps %%xmm4, %%xmm4\n"
+
+ "\tsub $20, %%ecx\n"
+
+ ".mul20_loo...
2013 Sep 26
1
[LLVMdev] Register scavenger and SP/FP adjustments
...on [SP-2056]
>> fi#2: size=4, align=4, at location [SP-4]
>> fi#3: size=4, align=4, at location [SP-8]
>> Constant Pool:
>> cp#0: -2048, align=4
>> cp#1: 2048, align=4
>>
>> BB#0: derived from LLVM BB %entry
>> Live Ins: %R4 %LR
>> tPUSH pred:14, pred:%noreg, %R4<kill>, %LR<kill>, %SP<imp-def>,
>> %SP<imp-use>; flags: FrameSetup
>> %vreg0<def> = tLDRpci <cp#0>, pred:14, pred:%noreg; flags:
>> FrameSetup tGPR:%vreg0
>> %SP<def,tied1> = tADDhirr %SP<ti...
2014 Aug 20
2
[LLVMdev] ARMv4T Copy Lowering
...g)
+ || ! ARM::tGPRRegClass.contains(DestReg)) {
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc)));
+ } else {
+ // This is the only way we can move low -> low for < v6.
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPUSH)))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPOP)))
+ .addReg(DestReg, getDefRegState(true));
+ }
}
void Thumb1InstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigne...
2013 Sep 26
0
[LLVMdev] Register scavenger and SP/FP adjustments
CallFrameSetupOpcode is a pseudo opcode like X86::ADJCALLSTACKDOWN64. That means when the code is expected to be called before the pseudo instructions are eliminated. I don't know why it's not the case for you. A quick look at PEI code indicates the pseudo's should not have been removed at the time when replaceFrameIndices are run.
Evan
On Sep 25, 2013, at 8:57 AM, Krzysztof
2013 Sep 25
2
[LLVMdev] Register scavenger and SP/FP adjustments
Hi All,
I'm dealing with a problem where the spill/restore instructions inserted
during scavenging span an adjustment of the SP/FP register. The result
is that despite the base register (SP/FP) being changed between the
spill and the restore, both store and load use the same immediate offset.
I see code in the PEI (replaceFrameIndices) that is supposed to track
the SP/FP adjustment: