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On Fri, 7 Feb 2014, Timothy B. Terriberry wrote: > Martin Storsjo wrote: >> This is required in order to build using the built-in assembler >> in clang. > > These patches break the gcc build (with "Error: bad instruction"). Ah, right, sorry about that. > Documentation I've seen is contradictory on which order ({cond}{size} or > {size}{cond}) is correct.

...t a/celt/arm/celt_pitch_xcorr_arm.s b/celt/arm/celt_pitch_xcorr_arm.s index 09917b1..598e45b 100644 --- a/celt/arm/celt_pitch_xcorr_arm.s +++ b/celt/arm/celt_pitch_xcorr_arm.s @@ -309,7 +309,7 @@ xcorr_kernel_edsp_process4_done SUBS r2, r2, #1 ; j-- ; Stall SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0) - LDRGTH r14, [r4], #2 ; r14 = *x++ + LDRHGT r14, [r4], #2 ; r14 = *x++ SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1) SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2) SMLABT r9,...

..., r2 = y, r3 = N ldr r4, [sp, #40] @ r4 = mem, r5 = ord cmp r5, #10 beq .order_10 cmp r5, #8 beq .order_8 ldmia sp!, { r4-r11, pc } @ Mon-supported order, return @ TODO: try using direct form 1 filtering .order_8: ldmia r4, { r5-r12 } @ r5-r12 = mem[0..7] 0: ldrsh r14, [r0], #2 add r5, r5, #4096 @ Rounding constant str r0, [sp,#-4]! @ push r0 add r14, r14, r5, asr #13 @ (mem[0] + 4096) >> 13 + x[i] mov r5, #0x7f00 orr r5, r5, #0xff @ r...

...t a/celt/arm/celt_pitch_xcorr_arm.s b/celt/arm/celt_pitch_xcorr_arm.s index 09917b1..3c4b950 100644 --- a/celt/arm/celt_pitch_xcorr_arm.s +++ b/celt/arm/celt_pitch_xcorr_arm.s @@ -309,7 +309,7 @@ xcorr_kernel_edsp_process4_done SUBS r2, r2, #1 ; j-- ; Stall SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0) - LDRGTH r14, [r4], #2 ; r14 = *x++ + LDRHGT r14, [r4], #2 ; r14 = *x++ SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1) SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2) SMLABT r9,...

..., %reg1599, %mreg23<imp-def,dead> ; srcLine 0 Virt folded mapped NewMI 0x92450c0: ADD64mr <fi#184>, 1, %reg0, 0, %reg1599, %mreg23<imp-def,dead> ; srcLine 0 to %reg2613 ##### %reg1618 is what we care about here. The final register map looks like this: ##### [%reg2561 -> R12] [%reg2562 -> R14] [%reg2563 -> R12] [%reg2564 -> R12] [%reg2565 -> R12] [%reg2618 -> R12] [%reg2561 -> fi#165] [%reg2562 -> fi#165] [%reg2563 -> fi#165] [%reg2564 -> fi#165] [%reg2565 -> fi#165] [%reg2618 -> fi#184] ##### Now LocalSpiller comes along to do its wo...

...s while testing it for the backend i'm currently developing, but it produces exactly the same code for other targets: march = msp430: push.w r11 push.w r10 push.w r9 push.w r8 mov.w r14, r11 mov.w r15, r10 ; store a mov.w r13, r15 mov.w r12, r14 ; pass b call #msin mov.w r15, r9 mov.w r14, r8 ; store msin(b) mov.w r10, r15 mov.w r11, r14 ; pass a call #mcos mov.w r9, r13 ; pass msin(b) mov.w r8, r12 call #mdiv pop.w r8 pop.w r9 pop.w r10 pop...

Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2. It has 12 regular registers (R0 - R12), and R8 - R12 are used. I can generate mov instruction that from/ R8-R12 to/from R0-R6. From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot use them arbitrarily....

Hi, Chris (cc) and I try to get the SGE master monitor work with Apple Leopard dtrace. Unfortunately we are stuck with the error msg below. Anyone having an idea what could be the cause? What I can rule out as cause is function inlining for the reasons explained below. Background information on SGE master monitor implementation is under http://wiki.gridengine.info/wiki/index.php/Dtrace

Hello, I am wondering whether there is a way to test whether two non-independent correlation coefficients are significantly different, in R? I have an experimentally measure variable Y, and two different variables X1, and X2, which are predictions of Y that were predicted using two different computational models. I would like to see whether the correlation of Y and X1, and Y and X2 is

...4 b8 41 8b 45 RSP: 0018:ffffa497c1977c10 EFLAGS: 00010202 RAX: 0000000000000030 RBX: 0000000000000000 RCX: 00000000094cfe23 RDX: 00000000094cfe1b RSI: 00000000094cfe1b RDI: 0000000000029660 RBP: 0000000000000060 R08: ffffa497c1b91000 R09: ffff9a53d535ee78 R10: 0000000000000001 R11: 00000000000003ff R12: 00000001067fdb37 R13: ffff9a53f5c07480 R14: 0000000000000dc0 R15: ffff9a53f5c07480 FS: 00007fb65997f700(0000) GS:ffff9a53f6cc0000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00000001067fdb67 CR3: 000000013d42d000 CR4: 00000000000406e0 Call Trace: nouveau_f...

...8))]>, Sched<[WriteALU]>; ~Craig On Sun, Apr 14, 2019 at 12:21 PM Jie Zhou <jzhou41 at cs.rochester.edu<mailto:jzhou41 at cs.rochester.edu>> wrote: Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2. It has 12 regular registers (R0 - R12), and R8 - R12 are used. I can generate mov instruction that from/ R8-R12 to/from R0-R6. From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html<https://urldefense.proofpoint.com/v2/url?u=http-3A__infocenter.arm.com_help_index.jsp-3Ftopic-3D_com.ar...

...ter code, or should I rather go to the code generator and try to add an optimization pass ? Thanks for any feedback. Ciao Nat! P.S. In case someone is interested, here is the assembler code and the IR that produced it. Relevant LLVM generated x86_64 assembler portion with -Os ~~~ testq %r12, %r12 je LBB0_5 ## BB#1: movq -8(%r12), %rcx movq (%rcx), %rax movq -8(%rax), %rdx andq %r15, %rdx cmpq %r15, (%rax,%rdx) je LBB0_2 ## BB#3: addq $8, %rcx jmp LBB0_4 LBB0_2: leaq 8(%rdx,%rax), %rcx LBB0_4: movq %r12, %rdi movq %r15, %rsi movq %r14, %rdx callq *(%rcx) movq %rax, %rbx...

...p instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I would get adds r0, 4 rather than adds r8, 4. Similar problems happen to push and pop instructions. I can create a push/pop if the register list only contains registers R0...

On 10 October 2014 12:48, Renato Golin <renato.golin at linaro.org> wrote: > 0x0014b494 <+192>: andeq r1, r0, r4, asr #23 > 0x0014b498 <+196>: andseq r8, r2, r12, lsl #24 > 0x0014b49c <+200>: andeq r1, r0, r12, ror r7 > 0x0014b4a0 <+204>: ; <UNDEFINED> instruction: 0x00128bd0 > => 0x0014b4a4 <+208>: ; <UNDEFINED> instruction: 0xfff99bda For context, the code is: 0x001d8e5c <+232>: mov r0, r4...

On Fri, 12 May 2006, Ralph Corderoy wrote: >> If you don't *know* that all (e.g.) function pointers to this code are >> dead (which means that execution could come back to the function), you >> should use the ExecutionEngine::recompileAndRelinkFunction(F) method. > > recompileAndRelinkFunction() overwrites the old machine code with a > branch to the new. Is it

...e bytes, PowerPC 16, > > PPC should be 4 bytes in the normal case. It is up to the backend to > implement this API correctly... if it doesn't, that's a bug: please > report it! No, EmitBranchToAt() always emits 16 bytes. AtI[0] = BUILD_LIS(12, Addr >> 16); // lis r12, hi16(address) AtI[1] = BUILD_ORI(12, 12, Addr); // ori r12, r12, low16(address) AtI[2] = BUILD_MTCTR(12); // mtctr r12 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl but I understand now how startFunctionStub() is given StubSize and on PowerPC it's 16 so there...

...value = -2048; > out[i]=value; > } > > I used opt -O3 and llc -O3 -march=arm -regalloc=greedy, and here is the code that is generated for the loop body (and two instructions that set a loop-invariant mask beforehand), with some comments of mine: > > mov r12, #255 > orr r12, r12, #65280 > LBB1_1: > ldrsh r3, [r1] # loads a short that is sign-extended to 32 bits > mov r4, lr > cmp r3, #2048 > bge .LBB1_3 > and r4, r3, r12 # m...

https://bugs.freedesktop.org/show_bug.cgi?id=98506 Bug ID: 98506 Summary: Pagefault in gf100_vm_flush Product: xorg Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at lists.freedesktop.org

...be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to come from the IfConvertion MachinePass. Here's is what it looks like before and after. > #BEFORE IfConversion MachinePass > > BB#7: > Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12 > Predecessors according to CFG: BB#5 BB#6 > STRBi12 %R5, %R6<kill>, 0, pred:14, pred:%noreg; mem:ST1[%cond.i23.i.i.i] > %R6<def> = LDRBi12 %R7, 0, pred:14, pred:%noreg; mem:LD1[%15](align=4) > %R3<def> = EORri %R6, 254, pred:14, pred:%noreg, opt:%noreg > %R3<d...

Hi the appended IR code does not optimize to my liking :) this is the interesting part in x86_64, that got produced via clang -Os: --- movq -16(%r12), %rax movl -4(%rax), %ecx andl $2298949, %ecx ## imm = 0x231445 cmpq $2298949, (%rax,%rcx) ## imm = 0x231445 leaq 8(%rax,%rcx), %rax cmovneq %r15, %rax movl $2298949, %esi ## imm = 0x231445 movq %r12, %rdi movq %r14, %rdx callq *(%rax) --- and clang -O3: --- movq...