llvm dev - Jun 2017 - Wide load/store optimization question

Hi,
Same here, my backend only has 64bit load/store. But i still use 64bit virt regs
and expand/declare missing instructions by myself. 
I'll try looking into sparc backend, thanks. Also, only after writing this
post I found a bunch of built-in transforms. Still trying to understand how to
use those.
By the way, constraint-wise (alignment), is there any difference between virt
regclass and regtuple?
Best regards,Petr


Отправлено со смартфона Samsung Galaxy.
-------- Исходное сообщение --------От: 陳韋任 <chenwj.cs97g at
g2.nctu.edu.tw> Дата: 16.06.17  22:03  (GMT+02:00) Кому: tstellar at
redhat.com Копия: Peter Bel <upcfrost at gmail.com>, LLVM Developers
Mailing List <llvm-dev at lists.llvm.org> Тема: Re: [llvm-dev] Wide
load/store optimization question
One thing you can do is define a register class that is made up of register

tuples e.g. r0r1, r2r3, etc., and use that register class for the 64-bit

load/store instructions.  This will allow you to do the load/store

merging before register allocation without the register constraints.
​Our backend only support load/store for i64 type, hence i64 is not legal for
us.I guess Peter's Epiphany arch has similar situation.​
IIRC, LLVM expand load i64 to two load i32. Right now, we have to customlowering
load i64 to load v2i32, then map v2i32 to the tuple register (similarto Sparc
backend). How can we use the tuple register for those two i32? ​Any existing
example?
Regards,chenwj​
-- 
Wei-Ren Chen (陳韋任)
Homepage: https://people.cs.nctu.edu.tw/~chenwj

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2017-06-17 4:36 GMT+08:00 upcfrost <upcfrost at gmail.com>:
> Hi,
>
> Same here, my backend only has 64bit load/store. But i still use 64bit
> virt regs and expand/declare missing instructions by myself.
>
> I'll try looking into sparc backend, thanks. Also, only after writing
this
> post I found a bunch of built-in transforms. Still trying to understand how
> to use those.
>
> By the way, constraint-wise (alignment), is there any difference between
> virt regclass and regtuple?
>
​I guess no. ​Tom?

-- 
Wei-Ren Chen (陳韋任)
Homepage: https://people.cs.nctu.edu.tw/~chenwj
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> On Jun 16, 2017, at 2:43 PM, 陳韋任 via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> 
> 
> 2017-06-17 4:36 GMT+08:00 upcfrost <upcfrost at gmail.com
<mailto:upcfrost at gmail.com>>:
> Hi,
> 
> Same here, my backend only has 64bit load/store. But i still use 64bit virt
regs and expand/declare missing instructions by myself.
> 
> I'll try looking into sparc backend, thanks. Also, only after writing
this post I found a bunch of built-in transforms. Still trying to understand how
to use those.
> 
> By the way, constraint-wise (alignment), is there any difference between
virt regclass and regtuple?
That question makes no sense.
- Every virtual register has a register class assigned.
- You can construct special register classes that represent register tuples so
that when the allocator chooses an entry from that register class it really has
choosen a tuple of machine registers (even though it looks like a single
register with funny aliasing as far as llvm codegen is concerned).

- Matthias
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