llvm dev - May 2017

Wednesday May 31 2017
TimeRepliesSubject
8:04PM 0 Handling native i16 types in clang and opt
6:10PM 1 restrict pointer support in LLVM 4.0
5:57PM 1 Enable STATISTIC all the time again?
5:44PM 2 Enable STATISTIC all the time again?
4:23PM 1 Request for local llvm source code coverage for developers
4:18PM 0 Request for local llvm source code coverage for developers
3:57PM 3 [RFC] Making -mcpu=generic the default for ARM armv7a and arm8a rather than -mcpu=cortex-a8 or -mcpu=cortex-a53
3:23PM 2 [RFC] Making -mcpu=generic the default for ARM armv7a and arm8a rather than -mcpu=cortex-a8 or -mcpu=cortex-a53
3:17PM 2 Enable STATISTIC all the time again?
3:02PM 1 [RFC] Making -mcpu=generic the default for ARM armv7a and arm8a rather than -mcpu=cortex-a8 or -mcpu=cortex-a53
2:48PM 1 Enable STATISTIC all the time again?
2:45PM 2 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
2:39PM 3 Enable STATISTIC all the time again?
1:35PM 2 [RFC] Making -mcpu=generic the default for ARM armv7a and arm8a rather than -mcpu=cortex-a8 or -mcpu=cortex-a53
1:33PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
1:21PM 0 [GSoC][clang] Bash completion for clang project
1:13PM 2 Buildbots timing out on full builds
12:57PM 3 [RFC] Making -mcpu=generic the default for ARM armv7a and arm8a rather than -mcpu=cortex-a8 or -mcpu=cortex-a53
12:48PM 1 Buildbots timing out on full builds
12:47PM 0 When a libcall will be generated?
11:06AM 2 Running lit (googletest) tests remotely
8:21AM 1 Buildbots timing out on full builds
3:20AM 0 Get elements from a getelementptr constant expression
2:13AM 0 Get elements from a getelementptr constant expression
1:35AM 0 constant pool
 
Tuesday May 30 2017
TimeRepliesSubject
11:01PM 0 LLVM buildmaster will be updated and restarted tonight
11:00PM 1 Should we split llvm Support and ADT?
10:54PM 1 Should we split llvm Support and ADT?
10:53PM 1 Missing symbol __executable_start on Android when linking with LLD
10:52PM 1 Should we split llvm Support and ADT?
10:49PM 3 Should we split llvm Support and ADT?
10:49PM 1 [atomics][AArch64] Possible bug in cmpxchg lowering
10:40PM 1 [atomics][AArch64] Possible bug in cmpxchg lowering
10:29PM 2 [atomics][AArch64] Possible bug in cmpxchg lowering
9:31PM 2 Should we split llvm Support and ADT?
9:29PM 1 Should we split llvm Support and ADT?
9:28PM 1 Should we split llvm Support and ADT?
9:27PM 1 Should we split llvm Support and ADT?
8:59PM 1 Should we split llvm Support and ADT?
8:57PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
8:50PM 3 Should we split llvm Support and ADT?
8:21PM 1 Should we split llvm Support and ADT?
8:16PM 1 Should we split llvm Support and ADT?
8:04PM 1 llvm::GlobalVariable usage (newbie question)
7:58PM 1 llvm::GlobalVariable usage (newbie question)
7:52PM 3 Should we split llvm Support and ADT?
7:39PM 1 llvm::GlobalVariable usage (newbie question)
7:05PM 2 Should we split llvm Support and ADT?
6:59PM 1 Missing symbol __executable_start on Android when linking with LLD
6:51PM 1 Missing symbol __executable_start on Android when linking with LLD
6:38PM 0 Instrumenting source, unresolved external function
6:05PM 1 Should we split llvm Support and ADT?
5:07PM 3 RFC: Replace usage of Alias Set Tracker with MemorySSA in LICM
4:58PM 1 Request for comments on optimizing assembler
4:56PM 1 Dumping the Vtable
4:48PM 1 Missing symbol __executable_start on Android when linking with LLD
4:28PM 1 Request for comments on optimizing assembler
4:16PM 1 Enable vectorizer-maximize-bandwidth by default?
4:00PM 1 Request for comments on optimizing assembler
2:42PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
1:56PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
1:40PM 1 [cfe-dev] LLVM 4.0.1-rc1 has been tagged
1:01PM 2 Pseudo-instruction that overwrites its input register
10:18AM 1 Communication between Clang Sema and the Clang Codegen...
9:58AM 1 LLVM Social - Paris: June 14th, 2017
9:06AM 1 The state of ARMConstantIslandPass in 4.0.[01]
9:00AM 0 Enable vectorizer-maximize-bandwidth by default?
8:39AM 3 Enable vectorizer-maximize-bandwidth by default?
8:38AM 0 JIT - Exception Handling under Windows
8:14AM 1 Enable vectorizer-maximize-bandwidth by default?
7:58AM 3 Enable vectorizer-maximize-bandwidth by default?
7:34AM 1 The state of ARMConstantIslandPass in 4.0.[01]
4:12AM 1 memcmp code fragment
3:43AM 1 Pseudo-instruction that overwrites its input register
1:14AM 3 [frontend-dev][beginner] Allocation of structures
 
Monday May 29 2017
TimeRepliesSubject
11:20PM 0 June LLVM bay-area social is this Thursday!
10:27PM 1 The state of ARMConstantIslandPass in 4.0.[01]
9:41PM 2 The state of ARMConstantIslandPass in 4.0.[01]
9:27PM 0 Request for comments on optimizing assembler
8:46PM 0 Print 128 bit value at runtime using printf
7:17PM 1 Print 128 bit value at runtime using printf
5:52PM 2 Should we split llvm Support and ADT?
5:35PM 1 Should we split llvm Support and ADT?
5:22PM 2 Should we split llvm Support and ADT?
4:51PM 0 LLVM Weekly - #178, May 29th 2017
4:25PM 2 Should we split llvm Support and ADT?
12:20PM 1 Dumping the Vtable
8:06AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
7:33AM 0 Where are the AArch64 buildbots?
5:07AM 1 Status of move to github
3:54AM 1 Should we split llvm Support and ADT?
 
Sunday May 28 2017
TimeRepliesSubject
9:50PM 0 [RFC] RISC-V backend
4:35PM 0 [RFC] RISC-V backend
3:51PM 0 llvm 3.9 CallGraphSCCPass results for C++ user defined type's constructor
3:25PM 1 Should we split llvm Support and ADT?
10:04AM 1 Pseudo-instruction that overwrites its input register
7:07AM 1 Pseudo-instruction that overwrites its input register
6:27AM 1 Pseudo-instruction that overwrites its input register
12:09AM 0 Handy file storage for LLD/ELF --reproduce
 
Saturday May 27 2017
TimeRepliesSubject
7:54PM 2 Should we split llvm Support and ADT?
7:50PM 1 Should we split llvm Support and ADT?
7:04PM 1 Finding nearest store to a variable
6:02PM 1 Should we split llvm Support and ADT?
3:44PM 0 Question
3:21PM 1 Merge two Attribute lists
2:34PM 1 Support for non-concrete types in LLVM
3:21AM 1 Should we split llvm Support and ADT?
3:06AM 2 Should we split llvm Support and ADT?
1:48AM 1 Should we split llvm Support and ADT?
1:36AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
12:59AM 3 Should we split llvm Support and ADT?
12:56AM 1 Should we split llvm Support and ADT?
12:47AM 3 Should we split llvm Support and ADT?
 
Friday May 26 2017
TimeRepliesSubject
9:27PM 2 Poison/Undef at CodeGen level Was: [poison] is select-of-select to logic+select allowed?
9:02PM 1 Poison/Undef at CodeGen level Was: [poison] is select-of-select to logic+select allowed?
8:02PM 2 Poison/Undef at CodeGen level Was: [poison] is select-of-select to logic+select allowed?
6:11PM 1 Running lit (googletest) tests remotely
6:09PM 0 Test failures sanstats/elf.test & ClangdVFSTest
4:54PM 1 Scope differentiate.
4:07PM 1 [compiler-rt] '-fprofile-generate' and embedded systems
3:45PM 0 Moving instructions from source Basic Block to dest Basic Block
3:17PM 3 Running lit (googletest) tests remotely
2:57PM 0 Printing out a 128 bit decimal
12:39PM 1 Moving instructions from source Basic Block to dest Basic Block
10:33AM 1 Why svn co of clang is not working?
10:09AM 1 Printing out a 128 bit decimal
9:46AM 1 [RFC] Canonicalization of unsigned subtraction with saturation
8:48AM 0 UD and DU chains for LLVM IR before running mem2reg
8:10AM 1 Buildbots timing out on full builds
4:30AM 1 How to implement memory-memory instructions?
3:58AM 1 [cfe-dev] www-scripts Sphinx doc builder broken and needs intervention.
2:26AM 1 Bitcast between 2 different SDNode vector types
 
Thursday May 25 2017
TimeRepliesSubject
8:53PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
6:48PM 1 [cfe-dev] www-scripts Sphinx doc builder broken and needs intervention.
6:00PM 1 [cfe-dev] www-scripts Sphinx doc builder broken and needs intervention.
4:14PM 0 UD and DU chains for LLVM IR before running mem2reg
4:00PM 0 Get function pointers from VTable
3:39PM 1 Buildbots timing out on full builds
3:11PM 1 Buildbots timing out on full builds
2:07PM 1 [compiler-rt] '-fprofile-generate' and embedded systems
1:38PM 1 [compiler-rt] '-fprofile-generate' and embedded systems
1:12PM 1 [compiler-rt] '-fprofile-generate' and embedded systems
1:00PM 0 Question
11:54AM 1 UD and DU chains for LLVM IR before running mem2reg
9:09AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
8:33AM 3 Some questions about software pipeline in LLVM 4.0.0
6:58AM 1 [cfe-dev] www-scripts Sphinx doc builder broken and needs intervention.
6:19AM 1 www-scripts Sphinx doc builder broken and needs intervention.
5:04AM 1 memcmp code fragment
4:54AM 1 www-scripts Sphinx doc builder broken and needs intervention.
3:28AM 1 www-scripts Sphinx doc builder broken and needs intervention.
1:08AM 0 TableGen - Help to implement a form of gather/scatter operations for Mips MSA
12:17AM 1 GraphTraits dereferencing
 
Wednesday May 24 2017
TimeRepliesSubject
8:01PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
7:57PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
7:01PM 2 Request for comments on optimizing assembler
6:43PM 1 DebugInfo, Metadata usage
6:39PM 1 DebugInfo, Metadata usage
5:31PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
5:26PM 1 Buildbots timing out on full builds
4:31PM 1 Buildbots timing out on full builds
4:29PM 2 Status of move to github
3:09PM 1 memcmp code fragment
1:49PM 0 Missing symbols in libLLVM.so when built with clang-4.0
1:08PM 1 How exactly is datatype alignment determined?
1:00PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
10:22AM 1 How to build lldb-mi
8:46AM 1 Support for monomorphization
2:56AM 2 GraphTraits dereferencing
12:16AM 1 [RFC] CFI for indirect calls with ThinLTO
12:14AM 1 [RFC] CFI for indirect calls with ThinLTO
 
Tuesday May 23 2017
TimeRepliesSubject
11:39PM 1 [RFC] CFI for indirect calls with ThinLTO
11:20PM 2 JIT - Resolve obj file without a main
11:17PM 2 [lld][ELF] Add option to make .dynamic read only
10:19PM 1 [lld][ELF] Add option to make .dynamic read only
9:40PM 2 bugpoint, LLVM tools (opt, llc, etc), and symbolizing costs
9:02PM 1 bugpoint, LLVM tools (opt, llc, etc), and symbolizing costs
7:48PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
7:27PM 1 [poison] is select-of-select to logic+select allowed?
5:50PM 1 Buildbots timing out on full builds
5:37PM 1 [poison] is select-of-select to logic+select allowed?
4:27PM 2 [poison] is select-of-select to logic+select allowed?
4:16PM 2 [poison] is select-of-select to logic+select allowed?
3:46PM 1 dfsan options at the IR level
3:32PM 1 Insert function definition at the top of the module
2:46PM 1 LLVM Social Zurich - June 1st
2:13PM 1 Removing "fno-rtti" flag from llvm-config --cxxflags
1:25PM 1 [poison] is select-of-select to logic+select allowed?
12:29PM 2 Removing "fno-rtti" flag from llvm-config --cxxflags
12:18PM 1 Removing "fno-rtti" flag from llvm-config --cxxflags
10:16AM 2 [poison] is select-of-select to logic+select allowed?
7:33AM 0 [BranchProbabilityInfo] The sum of all branch probabilities is not equal to 1
5:38AM 0 LLVM APT Repo
 
Monday May 22 2017
TimeRepliesSubject
10:29PM 0 Scheduler: modelling long register reservations?
8:50PM 1 [poison] is select-of-select to logic+select allowed?
8:45PM 2 [poison] is select-of-select to logic+select allowed?
8:32PM 2 [poison] is select-of-select to logic+select allowed?
7:41PM 1 Optimizing diamond pattern in DAGCombine
7:33PM 1 [lld][ELF] Add option to make .dynamic read only
7:19PM 1 Optimizing diamond pattern in DAGCombine
7:18PM 1 How exactly is datatype alignment determined?
7:01PM 1 Optimizing diamond pattern in DAGCombine
6:39PM 1 Optimizing diamond pattern in DAGCombine
6:15PM 0 LLVM Weekly - #177, May 22nd 2017
6:07PM 1 Optimizing diamond pattern in DAGCombine
5:45PM 1 DebugInfo, Metadata usage
5:33PM 1 Computing loop trip counts with Scalar evolution
5:27PM 1 Handling native i16 types in clang and opt
5:12PM 1 How exactly is datatype alignment determined?
4:57PM 1 Enable vectorizer-maximize-bandwidth by default?
3:26PM 1 How exactly is datatype alignment determined?
3:08PM 1 How exactly is datatype alignment determined?
2:48PM 1 How exactly is datatype alignment determined?
2:30PM 1 Optimizing diamond pattern in DAGCombine
1:23PM 1 Memory accesses and determining aliasing at the MI level
1:14PM 1 DebugInfo, Metadata usage
12:55PM 1 How exactly is datatype alignment determined?
12:49PM 1 How exactly is datatype alignment determined?
12:31PM 1 Default Location of CUDA headers in Windows and macOS
11:26AM 1 The right usage of llvm::ArrayRef
9:42AM 1 Buildbots timing out on full builds
9:38AM 1 Buildbots timing out on full builds
9:22AM 2 Buildbots timing out on full builds
8:49AM 1 Buildbots timing out on full builds
8:46AM 0 Defining new type in LLVM
7:51AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
7:09AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
6:21AM 1 Optimizing diamond pattern in DAGCombine
5:18AM 0 Fwd: Default Location of CUDA headers in Windows and macOS
5:06AM 2 Default Location of CUDA headers in Windows and macOS
4:28AM 2 Default Location of CUDA headers in Windows and macOS
 
Sunday May 21 2017
TimeRepliesSubject
10:24PM 2 [llvm] r303387 - [InstCombine] add more tests for xor-of-icmps; NFC
10:21PM 0 Scheduler does not generate nops when getHazardType returns NoopHazard
10:11PM 2 RFC: A new llvm-dlltool driver and llvm-lib driver improvements
8:51PM 1 RFC: A new llvm-dlltool driver and llvm-lib driver improvements
4:02PM 1 [llvm] r303387 - [InstCombine] add more tests for xor-of-icmps; NFC
3:55PM 1 [llvm] r303387 - [InstCombine] add more tests for xor-of-icmps; NFC
2:05PM 1 RFC: A new llvm-dlltool driver and llvm-lib driver improvements
10:47AM 1 Why not alias aarch64-apple-ios to arm64-apple-ios
10:16AM 1 Buildbots timing out on full builds
8:22AM 2 Handling native i16 types in clang and opt
3:56AM 0 Can not require two user defined analysis pass at the same time (Unable to schedule pass)
 
Saturday May 20 2017
TimeRepliesSubject
11:43PM 1 Collectively dominance
6:58PM 2 Has anyone here considered using repo for the Git migration?
6:54PM 2 apt.llvm.org: Ubuntu Trusty update rate
3:42PM 1 Patch review wanted
1:35PM 1 Patch review wanted
12:12PM 0 Computing loop trip counts with Scalar evolution
11:22AM 1 [lld][ELF] Add option to make .dynamic read only
4:32AM 1 Clang Stage 1: cmake, RA, using system compiler (Check) - Build # 31591 - Failure!
2:52AM 2 Memory accesses and determining aliasing at the MI level
1:38AM 2 [lld][ELF] Add option to make .dynamic read only
 
Friday May 19 2017
TimeRepliesSubject
11:27PM 1 [llvm] r303387 - [InstCombine] add more tests for xor-of-icmps; NFC
11:11PM 3 [llvm] r303387 - [InstCombine] add more tests for xor-of-icmps; NFC
11:01PM 2 Enable vectorizer-maximize-bandwidth by default?
9:32PM 1 memcmp code fragment
9:24PM 0 LLVM buildmaster will be updated and restarted tonight
8:18PM 0 About cross-translational-unit taint checking
8:17PM 1 memcmp code fragment
8:06PM 1 memcmp code fragment
7:50PM 1 noinline changes between 3.8 and 4.0?
7:47PM 1 noinline changes between 3.8 and 4.0?
7:46PM 2 memcmp code fragment
7:42PM 1 noinline changes between 3.8 and 4.0?
6:13PM 1 LLVM.org (SVN, web) DOWNTIME May 20th (7AM CST -> 1PM CDT)
5:06PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
3:46PM 1 Which pass should be propagating memory copies
3:02PM 0 Why does `opt` not infer the data-layout based on the triple?
2:34PM 1 Buildbots timing out on full builds
2:29PM 1 Buildbots timing out on full builds
2:22PM 0 Building LLVM using AIX native compilers
2:21PM 0 Reminder: Deadline for submitting 4.0.1 merge requests is May 22
1:54PM 1 Buildbots timing out on full builds
1:44PM 1 When a libcall will be generated?
1:18PM 1 Enable vectorizer-maximize-bandwidth by default?
1:14PM 1 Buildbots timing out on full builds
8:33AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
5:28AM 1 i386 libraries
 
Thursday May 18 2017
TimeRepliesSubject
10:50PM 2 debug the LLVM instcombine pass
10:30PM 3 Enable vectorizer-maximize-bandwidth by default?
9:19PM 0 Function LICM for readonly, nocapture functions
8:18PM 1 LLVM Fortran front-end
6:30PM 1 Computing loop trip counts with Scalar evolution
5:09PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
4:27PM 1 Question about demanded bits analysis
3:47PM 1 Which pass should be propagating memory copies
3:04PM 1 Question about demanded bits analysis
2:41PM 1 Memory accesses and determining aliasing at the MI level
2:08PM 1 Replacing Branch Instructions in LLVM IR: what am I missing?
12:22PM 1 LLVM Fortran front-end
11:30AM 2 32 bit architecture build
8:50AM 1 [cfe-dev] Struct padding
8:39AM 1 [cfe-dev] Struct padding
8:32AM 1 [cfe-dev] Struct padding
8:15AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
8:14AM 1 [cfe-dev] Struct padding
8:03AM 1 [cfe-dev] Struct padding
7:51AM 1 Struct padding
7:47AM 1 Struct padding
7:15AM 1 Struct padding
7:10AM 1 LLVM Fortran front-end
7:06AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
6:26AM 1 LLVM Fortran front-end
1:53AM 1 Machine instruction verifier pass
12:11AM 1 Printing MachineBasicBlock in an order that follows the CFG of the MachineFunction
 
Wednesday May 17 2017
TimeRepliesSubject
8:44PM 1 [lld][ELF] Add option to make .dynamic read only
8:32PM 1 [lld][ELF] Add option to make .dynamic read only
8:18PM 1 Machine instruction verifier pass
8:11PM 1 [lld][ELF] Add option to make .dynamic read only
6:29PM 1 Machine instruction verifier pass
5:58PM 2 ThinLTO with Linux+ELF+Gold -- incorrectly dropping weak definitions.
5:42PM 1 ThinLTO with Linux+ELF+Gold -- incorrectly dropping weak definitions.
5:34PM 1 Can we start using std::to_string?
5:28PM 1 Which pass should be propagating memory copies
3:55PM 2 Which pass should be propagating memory copies
3:38PM 1 Which pass should be propagating memory copies
2:56PM 1 PSA: Parallel STL algorithms available in LLVM
2:41PM 1 LLVM Fortran front-end
2:38PM 1 PSA: Parallel STL algorithms available in LLVM
2:24PM 1 PSA: Parallel STL algorithms available in LLVM
2:03PM 1 JIT - Resolve obj file without a main
1:52PM 1 Can we start using std::to_string?
1:44PM 1 Can we start using std::to_string?
11:05AM 1 Can we start using std::to_string?
10:12AM 1 Can we start using std::to_string?
4:09AM 1 Which pass should be propagating memory copies
3:01AM 1 www-scripts Sphinx doc builder broken and needs intervention.
2:12AM 1 [lld][ELF] Add option to make .dynamic read only
1:08AM 1 [lld][ELF] Add option to make .dynamic read only
12:13AM 1 [lld][ELF] Add option to make .dynamic read only
 
Tuesday May 16 2017
TimeRepliesSubject
11:33PM 1 [RFC] CFI for indirect calls with ThinLTO
11:31PM 3 [lld][ELF] Add option to make .dynamic read only
11:25PM 1 [GreenDragon] Maintenance Notification
9:51PM 1 [IR question] Switching on pointers
9:33PM 1 [IR question] Switching on pointers
9:15PM 2 LLVM Fortran front-end
8:39PM 1 ld.lld on MacOS question
7:49PM 1 [RFC] Canonicalization of unsigned subtraction with saturation
7:28PM 1 Which pass should be propagating memory copies
6:58PM 1 Bug in TableGen RegisterBankEmitter
6:18PM 1 [RFC] Canonicalization of unsigned subtraction with saturation
6:16PM 1 Which pass should be propagating memory copies
5:59PM 1 Bug in TableGen RegisterBankEmitter
5:56PM 1 Which pass should be propagating memory copies
5:50PM 1 Which pass should be propagating memory copies
5:37PM 2 Which pass should be propagating memory copies
4:52PM 1 ThinLTO with Linux+ELF+Gold -- incorrectly dropping weak definitions.
4:45PM 1 [IR question] Switching on pointers
4:43PM 1 ThinLTO with Linux+ELF+Gold -- incorrectly dropping weak definitions.
4:36PM 1 JIT - Resolve obj file without a main
4:32PM 0 [IR question] Switching on pointers
4:24PM 1 ld.lld on MacOS question
4:14PM 1 Enable new inline cost heuristic for switch
3:57PM 1 Bug in TableGen RegisterBankEmitter
2:56PM 0 How to remove a memory slot while allocating a register
1:30PM 1 [RFC] Canonicalization of unsigned subtraction with saturation
12:06PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
11:48AM 1 [IR question] Switching on pointers
11:30AM 1 [RFC] Canonicalization of unsigned subtraction with saturation
9:48AM 0 autovectorization of outer loop
8:57AM 0 Using single register class in Pat conversion in XXXInstrInfo.td
7:22AM 1 Semi-automatically updating PHI Nodes
1:44AM 1 [RFC] CFI for indirect calls with ThinLTO
12:17AM 1 [RFC] CFI for indirect calls with ThinLTO
 
Monday May 15 2017
TimeRepliesSubject
9:04PM 1 Disabling DAGCombine's specific optimization
8:36PM 1 Disabling DAGCombine's specific optimization
8:31PM 0 [LLD] Linking static library does not resolve symbols as gold/ld
8:29PM 1 Disabling DAGCombine's specific optimization
6:52PM 1 LLVMHello doesn't work - Loadable modules
4:29PM 3 [IR question] Switching on pointers
4:23PM 0 LLVM Weekly - #176, May 15th 2017
4:20PM 1 ThinLTO with Linux+ELF+Gold -- incorrectly dropping weak definitions.
3:29PM 1 RFC: Representing unions in TBAA
2:09PM 1 LLVMHello doesn't work - Loadable modules
1:52PM 1 [cfe-dev] Reminder: 1 week left to submit merge requests for the 4.0.1
12:30PM 1 [cfe-dev] Reminder: 1 week left to submit merge requests for the 4.0.1
9:58AM 2 Using single register class in Pat conversion in XXXInstrInfo.td
9:26AM 1 Reminder: 1 week left to submit merge requests for the 4.0.1
8:13AM 1 Disabling DAGCombine's specific optimization
7:38AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
5:54AM 1 Disabling DAGCombine's specific optimization
2:00AM 1 RFC: Representing unions in TBAA
1:20AM 4 RFC: Representing unions in TBAA
 
Sunday May 14 2017
TimeRepliesSubject
9:39PM 1 RFC: Representing unions in TBAA
6:01PM 1 RFC: Representing unions in TBAA
5:49PM 1 RFC: Representing unions in TBAA
5:33PM 1 apt.llvm.org: Ubuntu Trusty update rate
5:20PM 1 RFC: Representing unions in TBAA
4:06PM 1 RFC: Representing unions in TBAA
3:37PM 1 RFC: Representing unions in TBAA
10:12AM 1 CrashRecoveryContext::getBacktrace
 
Saturday May 13 2017
TimeRepliesSubject
12:15AM 0 LLVM lab will be unavailable tomorrow for few hours
 
Friday May 12 2017
TimeRepliesSubject
10:31PM 1 RFC: SROA for method argument
8:46PM 1 Email list just for front end developers?
6:06PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
4:19PM 2 PSA: Parallel STL algorithms available in LLVM
4:14PM 2 PSA: Parallel STL algorithms available in LLVM
4:00PM 2 PSA: Parallel STL algorithms available in LLVM
3:34PM 2 How to get the textual representation of an IR instruction?
3:14PM 1 Funclet restrictions and Verifier
1:47PM 1 JIT - Resolve obj file without a main
1:45PM 0 Changing the Opcode of an Instruction
12:35PM 1 problem (and fix) with -fms-extensions
12:22PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
11:44AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
10:28AM 1 problem (and fix) with -fms-extensions
10:07AM 1 Email list just for front end developers?
10:01AM 1 problem (and fix) with -fms-extensions
7:52AM 2 PSA: Parallel STL algorithms available in LLVM
6:58AM 0 Email list just for front end developers?
6:34AM 1 ld.lld on MacOS question
3:03AM 2 Email list just for front end developers?
2:48AM 1 Email list just for front end developers?
1:53AM 1 FENV_ACCESS and floating point LibFunc calls
1:48AM 1 Alias analysis results
1:48AM 1 FENV_ACCESS and floating point LibFunc calls
1:30AM 2 FENV_ACCESS and floating point LibFunc calls
 
Thursday May 11 2017
TimeRepliesSubject
11:36PM 1 FENV_ACCESS and floating point LibFunc calls
10:51PM 1 Email list just for front end developers?
10:20PM 1 FENV_ACCESS and floating point LibFunc calls
9:06PM 1 FENV_ACCESS and floating point LibFunc calls
7:28PM 1 FENV_ACCESS and floating point LibFunc calls
6:53PM 1 ld.lld on MacOS question
6:45PM 1 Add more projects into Git monorepo
6:04PM 2 problem (and fix) with -fms-extensions
5:41PM 1 RFC: A new llvm-dlltool driver and llvm-lib driver improvements
5:37PM 1 ld.lld on MacOS question
4:40PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
4:34PM 1 RFC: Moving the module summary into the irsymtab
3:16PM 2 LLVMHello doesn't work - Loadable modules
11:01AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
10:48AM 1 Testing selection dag combines
10:14AM 1 Email list just for front end developers?
10:00AM 1 RFC: A new llvm-dlltool driver and llvm-lib driver improvements
8:50AM 2 Alias analysis results
8:48AM 2 [lld] adding new lld target to the backend
7:32AM 1 Upgrading Phabricator
6:44AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
5:14AM 1 PSA: Parallel STL algorithms available in LLVM
4:14AM 1 PSA: Parallel STL algorithms available in LLVM
3:36AM 2 PSA: Parallel STL algorithms available in LLVM
3:35AM 1 Add more projects into Git monorepo
3:08AM 1 PSA: Parallel STL algorithms available in LLVM
2:58AM 1 FENV_ACCESS and floating point LibFunc calls
2:21AM 1 Add more projects into Git monorepo
1:09AM 2 moving libfuzzer to compiler-rt?
12:37AM 1 PSA: Parallel STL algorithms available in LLVM
 
Wednesday May 10 2017
TimeRepliesSubject
11:57PM 1 FENV_ACCESS and floating point LibFunc calls
11:44PM 1 FENV_ACCESS and floating point LibFunc calls
11:43PM 1 moving libfuzzer to compiler-rt?
11:17PM 1 FENV_ACCESS and floating point LibFunc calls
8:58PM 1 Bug in TableGen RegisterBankEmitter
8:39PM 1 www-scripts Sphinx doc builder broken and needs intervention.
7:00PM 2 -speculative-execution moving load before store
5:41PM 0 New gcc6 builder with -DLLVM_ENABLE_WERROR=ON
3:58PM 1 Bug in TableGen RegisterBankEmitter
3:36PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
2:15PM 1 Bug in TableGen RegisterBankEmitter
12:38PM 1 Computing unique ID of IR instructions that can be mapped back
8:11AM 1 [OpenCL][AMDGPU] Using AMDGPU generated kernel code for OpenCL
7:16AM 1 autovectorization of outer loop
6:37AM 2 -speculative-execution moving load before store
5:57AM 1 www-scripts Sphinx doc builder broken and needs intervention.
5:23AM 1 Instruction selection for 'load' based on static vs. dynamic data
5:21AM 1 MBB reordering vs. MBB fall-through
5:09AM 0 specomp 2012
2:52AM 2 [SPIR-V] SPIR-V in LLVM
2:05AM 0 TableGen support for Intrinsics with multiple outputs
 
Tuesday May 9 2017
TimeRepliesSubject
11:53PM 1 AVX2 codegen
11:25PM 1 www-scripts Sphinx doc builder broken and needs intervention.
11:04PM 1 moving libfuzzer to compiler-rt?
10:51PM 1 [cfe-dev] JIT doens't resolve address - Resolve obj-Addresses?
10:00PM 1 moving libfuzzer to compiler-rt?
9:49PM 2 Enable new inline cost heuristic for switch
9:37PM 1 moving libfuzzer to compiler-rt?
9:19PM 1 moving libfuzzer to compiler-rt?
9:15PM 1 moving libfuzzer to compiler-rt?
8:56PM 1 moving libfuzzer to compiler-rt?
7:03PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
6:55PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
6:54PM 0 Clang UPC and UPC2C v3.9.1 Release
6:47PM 3 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
6:07PM 1 moving libfuzzer to compiler-rt?
5:55PM 2 moving libfuzzer to compiler-rt?
5:53PM 2 RFC: SROA for method argument
5:23PM 1 moving libfuzzer to compiler-rt?
4:47PM 1 lib/CodeGen/AsmPrinter/DwarfDebug.h:131: void llvm::DbgVariable::addMMIEntry(const llvm::DbgVariable&): Assertion `V.Var == Var && "conflicting variable"' failed.
4:06PM 1 Add more projects into Git monorepo
4:03PM 1 Add more projects into Git monorepo
3:59PM 1 Add more projects into Git monorepo
3:52PM 1 Build polly-amd64-linux Failure
3:17PM 1 Add more projects into Git monorepo
3:08PM 1 Build polly-amd64-linux Failure
3:06PM 1 Instruction selection for 'load' based on static vs. dynamic data
2:58PM 1 Add more projects into Git monorepo
2:28PM 2 Instruction selection for 'load' based on static vs. dynamic data
2:24PM 1 [cfe-dev] JIT doens't resolve address - Resolve obj-Addresses?
1:58PM 1 Weird LLVM pass effect
1:49PM 1 [OpenCL][AMDGPU] Using AMDGPU generated kernel code for OpenCL
1:16PM 1 Instruction selection for 'load' based on static vs. dynamic data
1:05PM 1 RFC: SROA for method argument
1:01PM 1 Instruction selection for 'load' based on static vs. dynamic data
1:00PM 0 LLVM Community at IIT-Madras and Chennai, India
12:47PM 1 Add more projects into Git monorepo
11:51AM 1 Instruction selection for 'load' based on static vs. dynamic data
10:41AM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
7:53AM 1 [SPIR-V] SPIR-V in LLVM
7:38AM 1 CrashRecoveryContext::getBacktrace
7:17AM 0 recognise DW_AT_SUN_amd64_parmdump dwarf attribute
5:19AM 1 Computing unique ID of IR instructions that can be mapped back
5:12AM 1 Computing unique ID of IR instructions that can be mapped back
2:34AM 1 Computing unique ID of IR instructions that can be mapped back
1:56AM 1 lib/CodeGen/AsmPrinter/DwarfDebug.h:131: void llvm::DbgVariable::addMMIEntry(const llvm::DbgVariable&): Assertion `V.Var == Var && "conflicting variable"' failed.
1:28AM 1 lib/CodeGen/AsmPrinter/DwarfDebug.h:131: void llvm::DbgVariable::addMMIEntry(const llvm::DbgVariable&): Assertion `V.Var == Var && "conflicting variable"' failed.
1:25AM 1 lib/CodeGen/AsmPrinter/DwarfDebug.h:131: void llvm::DbgVariable::addMMIEntry(const llvm::DbgVariable&): Assertion `V.Var == Var && "conflicting variable"' failed.
1:20AM 1 lib/CodeGen/AsmPrinter/DwarfDebug.h:131: void llvm::DbgVariable::addMMIEntry(const llvm::DbgVariable&): Assertion `V.Var == Var && "conflicting variable"' failed.
1:14AM 1 Computing unique ID of IR instructions that can be mapped back
12:40AM 1 Computing unique ID of IR instructions that can be mapped back
12:19AM 0 LLVM buildmaster will be updated and restarted tonight
 
Monday May 8 2017
TimeRepliesSubject
10:39PM 1 Handling invariant.groups with equality + marking it as experimental
9:23PM 2 Has anyone here considered using repo for the Git migration?
8:55PM 4 Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section
8:55PM 1 RFC: Element-atomic memory intrinsics
8:05PM 1 Add more projects into Git monorepo
8:00PM 1 ORC and MCJIT clients: Heads up, API breaking changes in the pipeline.
7:51PM 1 Add more projects into Git monorepo
7:08PM 1 RFC: Element-atomic memory intrinsics
6:57PM 1 Add more projects into Git monorepo
6:51PM 1 Handling invariant.groups with equality + marking it as experimental
6:38PM 1 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
6:36PM 1 Comparison with Statistic objects
6:22PM 1 RFC: Element-atomic memory intrinsics
6:05PM 2 moving libfuzzer to compiler-rt?
5:49PM 2 RFC: Element-atomic memory intrinsics
5:31PM 3 [SPIR-V] SPIR-V in LLVM
5:30PM 1 LibFuzzer syntax sugar flag
5:25PM 1 LLVM and Xeon Skylake v5
5:20PM 1 LLVM and Xeon Skylake v5
5:06PM 1 LLVM and Xeon Skylake v5
4:55PM 1 LLVM and Xeon Skylake v5
4:42PM 1 Get size of unwind information
4:32PM 1 LLVM and Xeon Skylake v5
4:21PM 1 LLVM and Xeon Skylake v5
3:54PM 0 Instruction selection for 'load' based on static vs. dynamic data
3:49PM 0 Instruction selection for 'load' based on static vs. dynamic data
2:54PM 1 RFC: Element-atomic memory intrinsics
2:54PM 1 Using !dereferenceable metadata on the result of llvm.read_register?
2:11PM 1 Instruction selection for 'load' based on static vs. dynamic data
12:47PM 1 [SPIR-V] SPIR-V in LLVM
12:36PM 0 LLVM Weekly - #175, May 8th 2017
9:43AM 1 [OpenCL][AMDGPU] Using AMDGPU generated kernel code for OpenCL
9:41AM 1 LLVM 4.0.1-rc1 has been tagged
6:33AM 1 Add more projects into Git monorepo
5:15AM 1 CrashRecoveryContext::getBacktrace
 
Sunday May 7 2017
TimeRepliesSubject
11:03PM 1 ORC and MCJIT clients: Heads up, API breaking changes in the pipeline.
10:16PM 0 [FFI] [OrcJIT] Status update on C FFI for OrcJIT?
8:39PM 0 Developers wanted: TrueBit is hiring!
7:56PM 1 Handling invariant.groups with equality + marking it as experimental
4:59PM 1 How does one match undef in tablegen?
4:44PM 1 How does one match undef in tablegen?
4:25PM 1 Idea for Open Project : Smarter way of dumping LLVM IR with -emit-after-all
3:39PM 2 Instruction selection for 'load' based on static vs. dynamic data
2:09PM 2 What is "splat" in BUILD_VECTOR?
1:43PM 2 Email list just for front end developers?
8:25AM 2 X86 disassembler fails to handle 0x66 prefix?
8:01AM 2 Add more projects into Git monorepo
7:40AM 1 X86 disassembler fails to handle 0x66 prefix?
7:22AM 1 X86 disassembler fails to handle 0x66 prefix?
7:07AM 2 Add more projects into Git monorepo
4:38AM 2 Email list just for front end developers?
3:11AM 1 What is "splat" in BUILD_VECTOR?
3:08AM 1 What is "splat" in BUILD_VECTOR?
2:37AM 1 [cfe-dev] JIT doens't resolve address - Resolve obj-Addresses?
 
Saturday May 6 2017
TimeRepliesSubject
9:55PM 1 Email list just for front end developers?
8:46PM 1 Email list just for front end developers?
8:15PM 1 Email list just for front end developers?
7:06PM 1 Email list just for front end developers?
6:31PM 1 Email list just for front end developers?
6:22PM 1 LLVM and Pthreads
5:57PM 1 ld.lld on MacOS question
4:55PM 1 Email list just for front end developers?
4:29PM 1 Email list just for front end developers?
4:01PM 1 Email list just for front end developers?
3:57PM 1 Email list just for front end developers?
3:22PM 1 LLVM and Pthreads
3:11PM 1 Email list just for front end developers?
3:07PM 2 Email list just for front end developers?
2:46PM 1 Build polly-amd64-linux Failure
11:16AM 1 LLVM and Pthreads
7:43AM 1 clang assembler keeps .Linfo_string symbols?
 
Friday May 5 2017
TimeRepliesSubject
11:56PM 1 load instruction to gather intrinsics
11:41PM 1 load instruction to gather intrinsics
11:10PM 1 load instruction to gather intrinsics
9:42PM 1 load instruction to gather intrinsics
9:25PM 0 LLVM buildmaster will be updated and restarted tonight
8:20PM 1 Some info about CALLSEQ_START/CALLSEQ_END
6:37PM 1 LLVM 4.0.1-rc1 has been tagged
5:27PM 1 problem with non-allocatable register classes
4:20PM 1 Computing unique ID of IR instructions that can be mapped back
3:55PM 1 Idea for Open Project : Smarter way of dumping LLVM IR with -emit-after-all
3:49PM 1 Idea for Open Project : Smarter way of dumping LLVM IR with -emit-after-all
3:44PM 1 Idea for Open Project : Smarter way of dumping LLVM IR with -emit-after-all
2:48PM 0 problem with non-allocatable register classes
1:54PM 1 Machine instruction verifier pass
6:28AM 1 I want to update WritingAnLLVMBackend document
2:34AM 1 problem with non-allocatable register classes
12:32AM 1 DWARF Fission + ThinLTO
12:01AM 1 DWARF Fission + ThinLTO
 
Thursday May 4 2017
TimeRepliesSubject
11:53PM 1 DWARF Fission + ThinLTO
11:47PM 2 Computing unique ID of IR instructions that can be mapped back
11:46PM 1 Is it a good idea to mark class as deprecated?
10:56PM 1 Problem with Polly build
6:51PM 2 Look up table in function section
6:45PM 1 RFC: Shrink wrapping vs SplitCSR
6:36PM 2 DWARF Fission + ThinLTO
6:22PM 1 DWARF Fission + ThinLTO
6:20PM 0 [cfe-dev] Improvements to std::find and std::count
6:08PM 2 Look up table in function section
5:36PM 1 Look up table in function section
4:48PM 1 Help with setting up ARM embedded clang + lld
4:14PM 1 [LLVM] Sparse set
3:44PM 1 copyPhysReg() with undef source operand (llvm-stress)
2:40PM 1 DWARF Fission + ThinLTO
2:22PM 1 DWARF Fission + ThinLTO
1:44PM 1 Handling invariant.groups with equality + marking it as experimental
11:34AM 1 [libfuzzer] Fallback to stat if d_type == DT_UNKNOWN in ListFilesInDirRecursive method
8:35AM 1 Problem with Polly build
2:51AM 1 DWARF Fission + ThinLTO
2:48AM 1 DWARF Fission + ThinLTO
2:43AM 2 DWARF Fission + ThinLTO
12:21AM 1 Late proposal for Warn if virtual calls are made from constructors or destructors
12:03AM 1 Should it be legal for two functions to have the same !dbg attachment?
 
Wednesday May 3 2017
TimeRepliesSubject
11:58PM 2 Should it be legal for two functions to have the same !dbg attachment?
9:59PM 1 DWARF Fission + ThinLTO
9:58PM 1 How to instrument a module to spit out the addresses of global variables during initialization?
9:10PM 1 moving libfuzzer to compiler-rt?
9:09PM 1 DWARF Fission + ThinLTO
9:00PM 2 DWARF Fission + ThinLTO
8:44PM 0 How to pass a StringRef to a function call inserted as instrumentation?
7:10PM 1 moving libfuzzer to compiler-rt?
7:04PM 5 [SPIR-V] SPIR-V in LLVM
6:59PM 1 moving libfuzzer to compiler-rt?
6:51PM 1 Help with setting up ARM embedded clang + lld
6:24PM 1 clang assembler keeps .Linfo_string symbols?
6:04PM 1 allocsize: change from 3.9 to 4.0
5:50PM 1 RFC: Shrink wrapping vs SplitCSR
5:16PM 1 clang assembler keeps .Linfo_string symbols?
5:12PM 1 clang assembler keeps .Linfo_string symbols?
4:17PM 1 clang assembler keeps .Linfo_string symbols?
3:19PM 1 [SPIR-V] SPIR-V in LLVM
3:01PM 1 clang assembler keeps .Linfo_string symbols?
2:46PM 0 Fwd: Unsupported relocation emitted by LLVM
12:36PM 2 I want to update WritingAnLLVMBackend document
10:52AM 1 Help with setting up ARM embedded clang + lld
9:46AM 1 RFC: Improving the performance of ItaniumDemangle
9:23AM 1 I want to update WritingAnLLVMBackend document
9:17AM 1 [LTO] -time-passes and libLTO
9:15AM 1 clang assembler keeps .Linfo_string symbols?
5:00AM 1 [LTO] -time-passes and libLTO
4:58AM 1 Adding Falcon to http://llvm.org/Users.html
4:53AM 1 Adding Falcon to http://llvm.org/Users.html
4:34AM 2 moving libfuzzer to compiler-rt?
4:23AM 1 Adding Falcon to http://llvm.org/Users.html
2:54AM 1 RFC: Shrink wrapping vs SplitCSR
1:25AM 0 Permissions for llvm-mirror - Setting up Libc++ Appveyor builders
1:18AM 1 moving libfuzzer to compiler-rt?
12:49AM 1 Runtime-configurable LLVM_DEFAULT_TARGET_TRIPLE by env var
12:26AM 2 Runtime-configurable LLVM_DEFAULT_TARGET_TRIPLE by env var
 
Tuesday May 2 2017
TimeRepliesSubject
11:28PM 2 moving libfuzzer to compiler-rt?
10:59PM 1 Help with setting up ARM embedded clang + lld
9:52PM 1 When to use auto instead of iterator/const_iterator?
7:26PM 2 moving libfuzzer to compiler-rt?
6:48PM 1 LLVM module attributes question
6:47PM 0 Bugzilla Account requests - Email bugs-admin@lists.llvm.org
6:43PM 1 LLVM module attributes question
4:25PM 1 [LTO] -time-passes and libLTO
4:24PM 1 When to use auto instead of iterator/const_iterator?
3:42PM 2 [LTO] -time-passes and libLTO
3:31PM 2 [LTO] -time-passes and libLTO
2:36PM 1 LLVM 4.0.1-rc1 has been tagged
1:55PM 1 [ARM/Thumb] Make a function in arm while in Thumb triple
1:47PM 2 [ARM/Thumb] Make a function in arm while in Thumb triple
1:36PM 1 When to use auto instead of iterator/const_iterator?
1:36PM 1 [SPIR-V] SPIR-V in LLVM
12:36PM 1 RFC: Stop using redundant PHI node entries for multi-edge predecessors
12:12PM 2 [ARM/Thumb] Make a function in arm while in Thumb triple
12:04PM 0 (RFC) JumpMaps: switch statement optimization
12:02PM 1 dragonegg support for latest versions of llvm
11:53AM 1 dragonegg support for latest versions of llvm
11:40AM 1 dragonegg support for latest versions of llvm
8:07AM 1 [SPIR-V] SPIR-V in LLVM
6:34AM 1 RFC: Stop using redundant PHI node entries for multi-edge predecessors
5:48AM 0 New optimization view in Compiler Explorer aka godbolt.org
5:28AM 2 Enabling exception handling in llvm pass
1:44AM 2 [SPIR-V] SPIR-V in LLVM
1:43AM 1 SCEV - Non liner induction variable Addrec expression
1:00AM 5 LLVM 4.0.1-rc1 has been tagged
12:48AM 1 [SPIR-V] SPIR-V in LLVM
 
Monday May 1 2017
TimeRepliesSubject
11:43PM 1 [SPIR-V] SPIR-V in LLVM
11:19PM 0 May LLVM bay-area social is this Thursday!
10:50PM 1 Problem with Polly build
10:47PM 0 GlobalISel BoF follow-up
10:27PM 1 Problem with Polly build
8:23PM 1 Marking a register as reserved midway through register allocation
7:45PM 2 RFC: Moving the module summary into the irsymtab
6:45PM 0 LLMV JIT AVX2 support
6:16PM 1 Problem with Polly build
6:06PM 1 Problem with Polly build
6:06PM 1 RFC: Moving the module summary into the irsymtab
5:58PM 1 Problem with Polly build
5:35PM 1 Help with setting up ARM embedded clang + lld
5:18PM 1 RFC: Stop using redundant PHI node entries for multi-edge predecessors
4:29PM 2 RFC: Stop using redundant PHI node entries for multi-edge predecessors
4:01PM 0 LLVM Opportunity: Synopsys Mountain View, CA
3:53PM 1 [SPIR-V] SPIR-V in LLVM
3:47PM 2 RFC: Stop using redundant PHI node entries for multi-edge predecessors
3:44PM 0 LLVM Opportunity With Synopsys Mountain View, CA
3:14PM 0 LLVM Weekly - #174, May 1st 2017
2:50PM 0 Possible stack corruption during call to JITSymbol::getAddress()
2:27PM 2 Add more projects into Git monorepo
2:11PM 1 Help with setting up ARM embedded clang + lld
1:31PM 1 Marking a register as reserved midway through register allocation
1:30PM 1 RFC #3: Improving license & patent issues in the LLVM community
10:48AM 1 RFC: Stop using redundant PHI node entries for multi-edge predecessors
10:02AM 1 [SPIR-V] SPIR-V in LLVM
8:28AM 1 [SPIR-V] SPIR-V in LLVM
8:01AM 2 [SPIR-V] SPIR-V in LLVM
7:19AM 1 Marking a register as reserved midway through register allocation