Displaying 20 results from an estimated 41255 matches for "store".
2013 Oct 24
4
[LLVMdev] Vectorizing alloca instructions
...le program:
define void @vector(i32 addrspace(1)* %out, i32 %index) {
entry:
%0 = alloca [4 x i32]
%x = getelementptr [4 x i32]* %0, i32 0, i32 0
%y = getelementptr [4 x i32]* %0, i32 0, i32 1
%z = getelementptr [4 x i32]* %0, i32 0, i32 2
%w = getelementptr [4 x i32]* %0, i32 0, i32 3
store i32 0, i32* %x
store i32 1, i32* %y
store i32 2, i32* %z
store i32 3, i32* %w
%1 = getelementptr [4 x i32]* %0, i32 0, i32 %index
%2 = load i32* %1
store i32 %2, i32 addrspace(1)* %out
ret void
}
My goal is to have this program transformed to the following:
define void @vector(i32 a...
2019 May 17
2
Semantics for non-byte-sized stores? (or whenever "store size in bits" is different than "size in bits")
It is possible to ask DataLayout about getTypeSizeInBits and also getTypeStoreSize.
And there is a table showing an example of what it could look like:
/// Size examples:
///
/// Type SizeInBits StoreSizeInBits AllocSizeInBits[*]
/// ---- ---------- --------------- ---------------
/// i1 1 8 8
/// i8...
2015 Dec 11
2
Optimization of successive constant stores
Hmm... found an interesting issue:
Given:
%2 = getelementptr inbounds %UodStructType* %0, i32 0, i32 0
store i8 1, i8* %2, align 8
%3 = getelementptr inbounds %UodStructType* %0, i32 0, i32 1
store i8 2, i8* %3, align 1
%4 = getelementptr inbounds %UodStructType* %0, i32 0, i32 2
store i8 3, i8* %4, align 2
%5 = getelementptr inbounds %UodStructType* %0, i32 0, i32 3
store i8 4, i8...
2016 Jan 29
5
Question about store with unaligned memory address
Hi Krzysztof,
Thanks for response.
The method is working almost of test cases which use load and store
instructions connected with chain. There is other situation. Let's
look at a example as follows:
typedef unsigned short int UV __attribute__((vector_size (8)));
void test (UV *x, UV *y) {
*x = *y / ((UV) { 4, 4, 4, 4 });
}
The target does not support vector type so CodeGen tries to split...
2018 Sep 10
2
Byte-wide stores aren't coalesced if interspersed with other stores
...ed for your convenience):
source_filename = "pg"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-linux-gnu"
define void @evalexpr_0_0(i8* align 8 noalias, i32* align 8 noalias) {
entry:
%a01 = getelementptr i8, i8* %0, i16 0
store i8 0, i8* %a01
; in the real case this also loads data
%b01 = getelementptr i32, i32* %1, i16 0
store i32 0, i32* %b01
%a02 = getelementptr i8, i8* %0, i16 1
store i8 0, i8* %a02
; in the real case this also loads data
%b02 = getelementptr i32, i32* %1, i16 1
store i32 0, i32* %b...
2013 Oct 24
0
[LLVMdev] Vectorizing alloca instructions
Hi Tom,
Thanks for working on this. The SLP-vectorizer thinks that %X %Y %Z and %W alias, so it tries to perform 4 scalar store operations (which is a bad idea). We need to figure out why AA thinks that X and Y may alias. Maybe there is a problem with the code that uses AA.
Thanks,
Nadav
On Oct 24, 2013, at 2:04 PM, Tom Stellard <tom at stellard.net> wrote:
> Hi,
>
> I've been playing around with...
2005 Jul 26
4
elegant solution to transform vector into percentages?
Hi,
I am looking for an elegant way to transform a vector into percentages of values
that meet certain criteria.
store<-c(1,1.4,3,1.1,0.3,0.6,4,5)
# now I want to get the precentages of values
# that fall into the categories <=M , >M & <=N , >N
# let
M <-.8
N <- 1.2
# In my real example I have many more of these cutoff-points
# What I did is:
out <- matrix(NA,1,3)
out[1,1] <- (...
2012 Feb 20
2
[LLVMdev] ARM opcode format
...i8* %v8) {
entry:
%litTemp = alloca i32
%v0_INTEGER = alloca i32
%v4_INTEGER = alloca i32
%v5_INTEGER = alloca i32
%v2_INTEGER = alloca i32
%v6_INTEGER = alloca i32
%v5_POINTER = alloca i8*
%v1_INTEGER = alloca i32
%v3_INTEGER = alloca i32
%v7_INTEGER = alloca i32
store i32 1, i32* %v7_INTEGER
store i32 1, i32* %v3_INTEGER
store i32 0, i32* %v1_INTEGER
%0 = getelementptr i8* %v8, i32 8
%1 = bitcast i8* %0 to i8**
%2 = load i8** %1
store i8* %2, i8** %v5_POINTER
store i32 0, i32* %v6_INTEGER
%3 = load i8** %v5_POINTER
%4 = getelementptr i...
2016 Jun 22
2
LLVM Backend Issues
...rate
floating point registers, not sure if this will pose any issue?
Thanks again for your time!
Jeff
jeff at ubuntu:~/code$ llc -debug-only=isel dft_gf_msp.ll
=== main
Initial selection DAG: BB#0 'main:entry'
SelectionDAG has 18 nodes:
t0: ch = EntryToken
t4: ch = store<ST4[%retval]> t0, Constant:i32<0>,
FrameIndex:i32<0>, undef:i32
t7: ch = store<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>,
undef:i32
t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>,
FrameIndex:i32<3>, undef:i32...
2015 Dec 11
2
Optimization of successive constant stores
...r the following:
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
%UodStructType = type { i8, i8, i8, i8, i32, i8* }
define void @test(%UodStructType*) {
%2 = getelementptr inbounds %UodStructType* %0, i32 0, i32 0
store i8 1, i8* %2, align 8
%3 = getelementptr inbounds %UodStructType* %0, i32 0, i32 1
store i8 2, i8* %3, align 1
%4 = getelementptr inbounds %UodStructType* %0, i32 0, i32 2
store i8 3, i8* %4, align 2
%5 = getelementptr inbounds %UodStructType* %0, i32 0, i32 3
store i8 4, i8...
2006 Mar 09
1
Missing fields in search result
Hello ferret users,
I have a problem with ferret dropping stored fields in the index.
Not all fields I want to store get stored, so they can be searched, but
can''t be retrieved in a search.
Index creation:
INDEX = Index::Index.new(:path => ''/home/gregor/wisa/index'',
:analyzer => Analysis::WhiteSpaceA...
2019 Jun 25
2
How to handle ISD::STORE when both operands are FrameIndex?
...;
wrote:
> On Mon, 24 Jun 2019 at 12:16, Gleb Popov via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > 1. Where does it come from? Can I do anything to make it not appear?
>
> It comes from something like:
>
> %ptr = alloca i8
> %var = alloca i8*
> store i8* %ptr, i8** %var
>
> and in general it's not possible to eliminate the combination.
>
Aha, thanks.
> > 2. If not, how do I change it so that the operand being stored would be
> first loaded into a register, and that register would be used instead?
>
> While the sto...
2018 Sep 11
2
Byte-wide stores aren't coalesced if interspersed with other stores
...target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
> > target triple = "x86_64-pc-linux-gnu"
> >
> > define void @evalexpr_0_0(i8* align 8 noalias, i32* align 8 noalias) {
> > entry:
> > %a01 = getelementptr i8, i8* %0, i16 0
> > store i8 0, i8* %a01
> >
> > ; in the real case this also loads data
> > %b01 = getelementptr i32, i32* %1, i16 0
> > store i32 0, i32* %b01
> >
> > %a02 = getelementptr i8, i8* %0, i16 1
> > store i8 0, i8* %a02
> >
> > ; in the real case...
2013 May 12
0
[LLVMdev] Predicated Vector Operations
On Thu, May 9, 2013 at 4:47 PM, <dag at cray.com> wrote:
> Chandler Carruth <chandlerc at google.com> writes:
>
> > What are the desired memory model semantics for a masked store?
> > Specifically, let me suppose a simplified vector model of <2 x i64> on
> > an i64-word-size platform.
> >
> > masked_store(<42, 42>, Ptr, <true, false>)
> >
> > Does this write to the entier <2 x i64> object stored at Ptr or not?
>...
2016 Jan 30
0
Question about store with unaligned memory address
I'm not clear, but it sounds like maybe your issue is not just alignment,
but that you have no 1/2-byte load or store operations at all on your
target?
Do you mean that to do any 2-byte store, even if it's naturally aligned,
you need to load the 4-byte word that contains it, replace the low or high
half as appropriate, and then use a 4-byte store to store back the modified
value?
On Fri, Jan 29, 2016 at 2:07...
2014 Jun 18
3
[LLVMdev] Wrong float value stored in LLVM IR code
Hi everyone,
I'm learning how to use LLVM API and JIT engine and I've come across
with an issue I haven't been able to figure out.
The problem I'm having is that the wrong float is being stored in a
float global variable.
The code snippet I use to generate the float value is as follow:
llvm::Type* type = // initialize with the global variable type;
std::string real_value = // initialized with the float value from
std input.
...
return ConstantFP::get(type,real_va...
2016 Aug 25
6
invariant.load metadata semantics
Hi Hal,
Hal Finkel via llvm-dev wrote:
> Some questions: Do we allow stores to these locations at all? Only if
I'd vote for disallowing stores to these locations, but if "stores
allowed only if the value is the same" is helpful in some situation
then I don't have specific reasons why that would be problematic.
> the value is the same? Must any chan...
2012 Feb 20
0
[LLVMdev] ARM opcode format
...i8* %v8) {
entry:
%litTemp = alloca i32
%v0_INTEGER = alloca i32
%v4_INTEGER = alloca i32
%v5_INTEGER = alloca i32
%v2_INTEGER = alloca i32
%v6_INTEGER = alloca i32
%v5_POINTER = alloca i8*
%v1_INTEGER = alloca i32
%v3_INTEGER = alloca i32
%v7_INTEGER = alloca i32
store i32 1, i32* %v7_INTEGER
store i32 1, i32* %v3_INTEGER
store i32 0, i32* %v1_INTEGER
%0 = getelementptr i8* %v8, i32 8
%1 = bitcast i8* %0 to i8**
%2 = load i8** %1
store i8* %2, i8** %v5_POINTER
store i32 0, i32* %v6_INTEGER
%3 = load i8** %v5_POINTER
%4 = getelementptr i...
2011 Aug 24
2
[LLVMdev] Assert on Large Zeroinitializer Store
Dear All,
I currently have one of my transforms creating the following store
instruction:
store [65536 x i8] zeroinitializer, [65536 x i8]* %buf.i, align 16
... which causes the SelectionDAG code to assert out:
Assertion failed: (ResNo < NumValues && "Illegal result number!"),
function getValueType, file
/Users/criswell/src/llvm/include/llvm/CodeG...
2016 Jan 29
2
Question about store with unaligned memory address
Hi All,
I have a question about store with unaligned memory address.
I am working on target which has only 4 byte aligned load and store
instruction and I am generating 2 load and store instructions to store
value on memory which the address is not aligned 4. I am doing it with
lowering store as follow:
1. make low and high addres...