Hello LLVM, The ARM target sometimes adds an instruction with a virtual register in eliminateFrameIndex(): https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp This looks late for a virtual register to appear. Where is this vreg made real? Thanks, -steve
----- Original Message -----> From: "Steve King" <steve at metrokings.com> > To: llvmdev at cs.uiuc.edu > Sent: Thursday, January 29, 2015 3:00:26 PM > Subject: [LLVMdev] creating a vreg in eliminateFrameIndex() > > Hello LLVM, > The ARM target sometimes adds an instruction with a virtual register > in eliminateFrameIndex(): > > https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp > > This looks late for a virtual register to appear. Where is this vreg > made real?It is made real by the register scavanger (see scavengeFrameVirtualRegs in lib/CodeGen/PrologEpilogInserter.cpp. -Hal> > Thanks, > -steve > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- Hal Finkel Assistant Computational Scientist Leadership Computing Facility Argonne National Laboratory
On 1/29/15 2:00 PM, Steve King wrote:> Hello LLVM, > The ARM target sometimes adds an instruction with a virtual register > in eliminateFrameIndex(): > > https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp > > This looks late for a virtual register to appear. Where is this vreg made real?The register scavenger should take care of such emergency post-RA register allocation. For thumb1, this happens in Thumb1RegisterInfo::saveScavengerRegister(): http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca Cheers, Jon> > Thanks, > -steve > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- Jon Roelofs jonathan at codesourcery.com CodeSourcery / Mentor Embedded
Thanks Jon and Hal for the helpful pointers. By returning true from requiresRegisterScavenging() and requiresFrameIndexScavenging(), LLVM handled all the scavenging effort. That is nearly painless for the target, so why do some targets seem to do scavenging on their own? When the scavenged register is loaded with a simple immediate, is it safe to search the BB and replace other uses of the same immediate with the reg? In my case this gives a code size reduction. The search would stop on finding another use of the scavenged register. Thanks, -steve On Thu, Jan 29, 2015 at 1:15 PM, Jonathan Roelofs <jroelofs.lists at gmail.com> wrote:> > > On 1/29/15 2:00 PM, Steve King wrote: >> >> Hello LLVM, >> The ARM target sometimes adds an instruction with a virtual register >> in eliminateFrameIndex(): >> >> >> https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp >> >> This looks late for a virtual register to appear. Where is this vreg made >> real? > > The register scavenger should take care of such emergency post-RA register > allocation. For thumb1, this happens in > Thumb1RegisterInfo::saveScavengerRegister(): > http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca > > > Cheers, > > Jon >> >> >> Thanks, >> -steve >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> > > -- > Jon Roelofs > jonathan at codesourcery.com > CodeSourcery / Mentor Embedded >