search for: ac73131381e7f5533f8e1e601f8e1c9ca

...for a virtual register to appear. Where is this vreg made real? The register scavenger should take care of such emergency post-RA register allocation. For thumb1, this happens in Thumb1RegisterInfo::saveScavengerRegister(): http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca Cheers, Jon > > Thanks, > -steve > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > -- Jon Roelofs jonathan at codesourcery.com C...

Hello LLVM, The ARM target sometimes adds an instruction with a virtual register in eliminateFrameIndex(): https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp This looks late for a virtual register to appear. Where is this vreg made real? Thanks, -steve

...r. Where is this vreg made >> real? > > The register scavenger should take care of such emergency post-RA register > allocation. For thumb1, this happens in > Thumb1RegisterInfo::saveScavengerRegister(): > http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca > > > Cheers, > > Jon >> >> >> Thanks, >> -steve >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/l...

...; real? > > > > The register scavenger should take care of such emergency post-RA > > register > > allocation. For thumb1, this happens in > > Thumb1RegisterInfo::saveScavengerRegister(): > > http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca > > > > > > Cheers, > > > > Jon > >> > >> > >> Thanks, > >> -steve > >> _______________________________________________ > >> LLVM Developers mailing list > >> LLVMdev at cs.uiuc.edu http://llvm.cs.u...