search for: armbaseregisterinfo

> I almost change all the instruction formats. It was a huge work. I am going > to compile and run it now. We have done the similar work[1] on this topic by gcc and we have start migrate our platform to LLVM. In my experience, you need to take care the follow part: * ARMBaseRegisterInfo::getRegPressureLimit * ARMBaseRegisterInfo::getRawAllocationOrder * CalleeSavedRegs * ARMFrameLowering::emitPrologue [1] Doubling the Number of Registers on ARM Processors http://aces.snu.ac.kr/interact-16/papers/interact-16-paper-1.pdf

I almost change all the instruction formats. It was a huge work. I am going to compile and run it now. Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer Engineering University of Wisconsin-Madison E-mail: yazdanbakhsh

Hello LLVM, The ARM target sometimes adds an instruction with a virtual register in eliminateFrameIndex(): https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp This looks late for a virtual register to appear. Where is this vreg made real? Thanks, -steve

Hi Duncan, > const unsigned* > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { > + bool ghcCall = false; > + > + if (MF) { > + const Function *F = MF->getFunction(); > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); > + } > This bit looks dubious. Why do you...

Hi Duncan, On 10/14/11 03:56 PM, Duncan Sands wrote: > Hi Karel, > >> > const unsigned* >> > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) >> const { >> > + bool ghcCall = false; >> > + >> > + if (MF) { >> > + const Function *F = MF->getFunction(); >> > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); >> >...

...n t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced? They're not allocated during CodeGen because of the Reserved.set(…) calls in ARMBaseRegisterInfo.cpp. That said, this inconsistency is probably wrong anyway (or at best an approximation to reality) because it affects what the assembler supports. For example ldrsb sp, [r0]! is allowed, but ldrsb sp, [r0] is forbidden. I think they should both be UNPREDICTABLE (though this is an understandabl...

Hi, I have a question about the definitions of t2LDRSB and t2LDRSB_PRE in ARMInstrThumb2.td : I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?

Hi Karel, >>> > const unsigned* >>> > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) >>> const { >>> > + bool ghcCall = false; >>> > + >>> > + if (MF) { >>> > + const Function *F = MF->getFunction(); >>> > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC...

Hi Karel, > > const unsigned* > > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { > > + bool ghcCall = false; > > + > > + if (MF) { > > + const Function *F = MF->getFunction(); > > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); > > + } > > > This b...

On 1/29/15 2:00 PM, Steve King wrote: > Hello LLVM, > The ARM target sometimes adds an instruction with a virtual register > in eliminateFrameIndex(): > > https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp > > This looks late for a virtual register to appear. Where is this vreg made real? The register scavenger should take care of such emergency post-RA register allocation. For thumb1, this happens in Thumb1RegisterInfo::saveScavengerRegister(): http://llvm.org/docs/doxygen/html/structl...

...om> wrote: > > > On 1/29/15 2:00 PM, Steve King wrote: >> >> Hello LLVM, >> The ARM target sometimes adds an instruction with a virtual register >> in eliminateFrameIndex(): >> >> >> https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp >> >> This looks late for a virtual register to appear. Where is this vreg made >> real? > > The register scavenger should take care of such emergency post-RA register > allocation. For thumb1, this happens in > Thumb1RegisterInfo::saveScavengerRegister(): > ht...

...and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced? > > They're not allocated during CodeGen because of the Reserved.set(…) calls in ARMBaseRegisterInfo.cpp. > > That said, this inconsistency is probably wrong anyway (or at best an approximation to reality) because it affects what the assembler supports. For example > ldrsb sp, [r0]! > is allowed, but > ldrsb sp, [r0] > is forbidden. I think they should both be UNPREDICTABLE (t...

...Steve King wrote: > >> > >> Hello LLVM, > >> The ARM target sometimes adds an instruction with a virtual > >> register > >> in eliminateFrameIndex(): > >> > >> > >> https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp > >> > >> This looks late for a virtual register to appear. Where is this > >> vreg made > >> real? > > > > The register scavenger should take care of such emergency post-RA > > register > > allocation. For thumb1, this happens in &gt...

Hello, today is the last day[1] when someone might ask for feature merge into the LLVM 3.0 release. I'd like to ask you to merge attached patch. This is implementation of GHC calling convention on ARM platform which is made by Stephen Blackheath with few additions by me. I hope that although the patch does not contain any test case, it still will be merged. The reason for this is that

...en it is called on a dbg_value machine instruction. Currently the XCore target replaces the frame index with the frame register and sets the next operand to the byte offset from the frame register. A quick glance at some of the other targets suggests this is the right thing to do (for example ARMBaseRegisterInfo::eliminateFrameIndex and Thumb1RegisterInfo::eliminateFrameIndex appear to handle dbg_value in exactly the same way). Unfortunately this results in an assertion firing in MachineFrameInfo::getObjectOffset(). This is due to CompileUnit::constructVariableDIE() passing the second operand of the...

...er/Release+Asserts/AArch64AsmParser.o differ: byte 250094, line 1056 ./lib/Target/AArch64/Disassembler/Release+Asserts/AArch64Disassembler.o ../../recurse2be/build/./lib/Target/AArch64/Disassembler/Release+Asserts/AArch64Disassembler.o differ: byte 275066, line 1803 ./lib/Target/ARM/Release+Asserts/ARMBaseRegisterInfo.o ../../recurse2be/build/./lib/Target/ARM/Release+Asserts/ARMBaseRegisterInfo.o differ: byte 51142, line 104 ./lib/Target/ARM/Release+Asserts/ARMISelDAGToDAG.o ../../recurse2be/build/./lib/Target/ARM/Release+Asserts/ARMISelDAGToDAG.o differ: byte 245280, line 1268 ./lib/Target/ARM/InstPrinter/Relea...

Hi Duncan, Karel, On 14 October 2011 08:22, Duncan Sands <baldrick at free.fr> wrote: > Hi Karel, > >>>> > const unsigned* >>>> > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) >>>> const { >>>> > + bool ghcCall = false; >>>> > + >>>> > + if (MF) { >>>> > + const Function *F = MF->getFunction(); >>>> > + ghcCall = (F ? F->getCallingCo...

Hello Tim, thanks for response ---------------------------------------- > Date: Mon, 20 Apr 2015 11:45:03 -0700 > Subject: Re: [LLVMdev] question about alignment of structures on the stack (arm 32) > From: t.p.northover at gmail.com > To: alexey.perevalov at hotmail.com > CC: llvmdev at cs.uiuc.edu > > On 20 April 2015 at 11:09, Alexey Perevalov > <alexey.perevalov at

...I found it working for example -    subq    $32, %rsp +    andq    $-8, %rsp +    subq    $24, %rsp ... and of course modified function body, but for arm nothing happened. I tried to understand what goes wrong in llvm, but too many layers of abstractions. Maybe that code exists, but condition from ARMBaseRegisterInfo::canRealignStack prevent its generation. BTW, I build llvm/clang 3.6 (it was impossible to build  latest version from HEAD ) and something changed ;) -    str    r1, [sp, #20] -    str    r2, [sp, #16] -    add    r1, sp, #16 -    orr    r2, r1, #4 +    str    r1, [sp, #16] +    str    r2, [sp, #...

Hi all, There's been a recent bootstrap failure that might be covered up because of another failure. I just wanted to point this out so that people can take a look: -bw Here's the failure from our buildbot: Assertion failed: (DestReg == VirtReg && "Unknown load situation!"), function RewriteMBB, file /Volumes/Sandbox/Buildbot/llvm/build.llvm-