Displaying 6 results from an estimated 6 matches for "thumb1registerinfo".
2015 Jan 29
0
[LLVMdev] creating a vreg in eliminateFrameIndex()
...> https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>
> This looks late for a virtual register to appear. Where is this vreg made real?
The register scavenger should take care of such emergency post-RA
register allocation. For thumb1, this happens in
Thumb1RegisterInfo::saveScavengerRegister():
http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca
Cheers,
Jon
>
> Thanks,
> -steve
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu...
2015 Jan 29
3
[LLVMdev] creating a vreg in eliminateFrameIndex()
Hello LLVM,
The ARM target sometimes adds an instruction with a virtual register
in eliminateFrameIndex():
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp
This looks late for a virtual register to appear. Where is this vreg made real?
Thanks,
-steve
2015 Jan 30
2
[LLVMdev] creating a vreg in eliminateFrameIndex()
.../llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>>
>> This looks late for a virtual register to appear. Where is this vreg made
>> real?
>
> The register scavenger should take care of such emergency post-RA register
> allocation. For thumb1, this happens in
> Thumb1RegisterInfo::saveScavengerRegister():
> http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca
>
>
> Cheers,
>
> Jon
>>
>>
>> Thanks,
>> -steve
>> _______________________________________________
>> LLVM Dev...
2015 Jan 30
0
[LLVMdev] creating a vreg in eliminateFrameIndex()
...t; >>
> >> This looks late for a virtual register to appear. Where is this
> >> vreg made
> >> real?
> >
> > The register scavenger should take care of such emergency post-RA
> > register
> > allocation. For thumb1, this happens in
> > Thumb1RegisterInfo::saveScavengerRegister():
> > http://llvm.org/docs/doxygen/html/structllvm_1_1Thumb1RegisterInfo.html#ac73131381e7f5533f8e1e601f8e1c9ca
> >
> >
> > Cheers,
> >
> > Jon
> >>
> >>
> >> Thanks,
> >> -steve
> >> __________...
2015 Jan 11
3
[LLVMdev] [RFC] [PATCH] add tail call optimization to thumb1-only targets
...Ins) {
+ MIB.addReg(ARM::R4, getDefRegState(true));
+ NumRegs = true;
+ }
+
+ // It's illegal to emit pop instruction without operands.
+ if (NumRegs)
+ MBB.insert(MBBI, &*MIB);
+ else
+ MF.DeleteMachineInstr(MIB);
+
+ if (IsLRIncludedInCSI) {
+ const Thumb1RegisterInfo *RegInfo =
+ static_cast<const Thumb1RegisterInfo *>
+ (MF.getSubtarget().getRegisterInfo());
+
+ // Re-adjust stack pointer for LR content still residing on the stack.
+ emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, 4);
+ }
+
+ MachineOperand &J...
2011 Oct 10
2
[LLVMdev] Expected behavior of eliminateFrameIndex() on dbg_value machine instructions
...ction.
Currently the XCore target replaces the frame index with the frame
register and sets the next operand to the byte offset from the frame
register. A quick glance at some of the other targets suggests this is
the right thing to do (for example
ARMBaseRegisterInfo::eliminateFrameIndex and
Thumb1RegisterInfo::eliminateFrameIndex appear to handle dbg_value in
exactly the same way).
Unfortunately this results in an assertion firing in
MachineFrameInfo::getObjectOffset(). This is due to
CompileUnit::constructVariableDIE() passing the second operand of the
dbg_value instruction (set to the byte offset...