llvm dev - Jul 2012 - [LLVMdev] How to disable register allocate optimization?

Hi everyone,

I am trying to expand one instruction into multiple instructions on MIPS.
For example, I try to expand:
	sh	src, imm(dst)
into:
(1)	sb	src, imm(dst)
(2)	srl	reg0, src, 8
(3)	sb	reg0, (imm+1)(dst)
Here, reg0 are created with createVirtualRegister.

However, instr(2) will not be emitted because reg0 is useless before reg0 is
defined in instr(3), it is wrong!
So how to prevent the expansion from being optimized?
Is there any method to disable register allocate optimization?

Thanks in advance.

Yang

It looks like you are not using the right overloaded version of function
BuildMI defined in MachineInstrBuilder.h.

The register operand added to instruction sb should be a use, not a def
operand. So this function should be called,

BuildMI(BB, dl, TII->get(Mips::SB)).addReg(tmpReg1)

instead of

BuildMI(BB, dl, TII->get(Mips::SB), tmpReg1)



On Sat, Jul 21, 2012 at 11:41 AM, Yang Yang <geraint0923 at gmail.com>
wrote:
> Hi everyone,
>
> I am trying to expand one instruction into multiple instructions on MIPS.
> For example, I try to expand:
>         sh      src, imm(dst)
> into:
> (1)     sb      src, imm(dst)
> (2)     srl     reg0, src, 8
> (3)     sb      reg0, (imm+1)(dst)
> Here, reg0 are created with createVirtualRegister.
>
> However, instr(2) will not be emitted because reg0 is useless before reg0
> is defined in instr(3), it is wrong!
> So how to prevent the expansion from being optimized?
> Is there any method to disable register allocate optimization?
>
> Thanks in advance.
>
> Yang
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
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Thank you very much for your help!

It really works.

I used to think the two version of the function BuildMI is the same, so I made
the mistake.
I think I understand now:
BuildMI with a register is to build an instruction with the register provided as
a destination,
and another version without register  is to build an instruction without
destination.

Thanks,
Yang

On Jul 24, 2012, at 3:36 AM, Akira Hatanaka wrote:
> It looks like you are not using the right overloaded version of function
BuildMI defined in MachineInstrBuilder.h.
> 
> The register operand added to instruction sb should be a use, not a def
operand. So this function should be called,
> 
> BuildMI(BB, dl, TII->get(Mips::SB)).addReg(tmpReg1)
> 
> instead of
> 
> BuildMI(BB, dl, TII->get(Mips::SB), tmpReg1)
> 
> 
> 
> On Sat, Jul 21, 2012 at 11:41 AM, Yang Yang <geraint0923 at
gmail.com> wrote:
> Hi everyone,
> 
> I am trying to expand one instruction into multiple instructions on MIPS.
> For example, I try to expand:
>         sh      src, imm(dst)
> into:
> (1)     sb      src, imm(dst)
> (2)     srl     reg0, src, 8
> (3)     sb      reg0, (imm+1)(dst)
> Here, reg0 are created with createVirtualRegister.
> 
> However, instr(2) will not be emitted because reg0 is useless before reg0
is defined in instr(3), it is wrong!
> So how to prevent the expansion from being optimized?
> Is there any method to disable register allocate optimization?
> 
> Thanks in advance.
> 
> Yang
> 
> 
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
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