search for: createvirtualregist

...omment on a patch like: diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 65ee3816f84..4780f6f0e59 100644 --- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -243,18 +243,21 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,      if (!VRBase && !IsClone && !IsCloned)        for (SDNode *User : Node->uses()) {          if (User->getOpcode() == ISD::CopyToReg &&              User->getOperand(2).getNode() == Node &&              User->getOperand(2).getRes...

...MachineOperand &RMO = UI.getOperand(); MachineInstr *RMI = &*UI; ++UI; MachineBasicBlock *RMBB = RMI->getParent(); if (RMBB == MBB) continue; const TargetRegisterClass* RC = mri_->getRegClass(Reg); unsigned NewVReg = mri_->createVirtualRegister(RC); MachineInstrBuilder MIB = BuildMI(*RMBB, RMI, RMI->getDebugLoc(), tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg); (*MIB).getOperand(0).setIsUndef(); RMO.setReg(NewVReg); RMO.setIsUndef(); RMO.setIsKill(); }...

...t;Register scavenger failed"); RS->setRegUsed(RegUnused0); It works but there are two issues: 1) I need to registers and RegScavenger only returns one. 2) I cannot unset the used register and I get spill slot error message when I ran out of the available registers. So I gave up and tried createVirtualRegister(): MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); const TargetRegisterClass *RC = &LASER::GNPRegsRegClass; unsigned Reg = RegInfo.createVirtualRegister(RC); But then I get the following error: MachineCopyPropagation.cpp:267: void anonymous}::MachineCopyPropagation::Co...

...UI.getOperand(); > MachineInstr *RMI = &*UI; > ++UI; > MachineBasicBlock *RMBB = RMI->getParent(); > if (RMBB == MBB) > continue; > const TargetRegisterClass* RC = mri_->getRegClass(Reg); > unsigned NewVReg = mri_->createVirtualRegister(RC); > MachineInstrBuilder MIB = > BuildMI(*RMBB, RMI, RMI->getDebugLoc(), > tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg); > (*MIB).getOperand(0).setIsUndef(); > RMO.setReg(NewVReg); > RMO.setIsUndef(); >...

Looks good. + unsigned temp; + if (is64bit) + temp = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); + else + temp = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); How about? const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : &PPC:G8RCRegClass; unsigned TmpReg = RegInfo.createVirtualRegister(RC); Evan On Jul 9, 2008, at 9:16 AM, G...

...rase); MBB_cond->addSuccessor(MBB_end); MBB_erase->addSuccessor(MBB_cond); MBB_erase->addSuccessor(MBB_end); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); unsigned regA = MRI.createVirtualRegister(AddrRegClass); unsigned regB = MRI.createVirtualRegister(AddrRegClass); unsigned regC = MRI.createVirtualRegister(AddrRegClass); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); // Check condition BuildMI(*MBB_cond, MBB_co...

I need to use ‘createVirtualRegister’ for a specific case in my ‘eliminateFrameIndex’ function implementation. However, whenever that code is executed, I get the assertion "MachineCopyPropagation should be run after register allocation!” at a later stage. I have seen that at least a couple of backend implementations (includin...

Hi everyone, I am trying to expand one instruction into multiple instructions on MIPS. For example, I try to expand: sh src, imm(dst) into: (1) sb src, imm(dst) (2) srl reg0, src, 8 (3) sb reg0, (imm+1)(dst) Here, reg0 are created with createVirtualRegister. However, instr(2) will not be emitted because reg0 is useless before reg0 is defined in instr(3), it is wrong! So how to prevent the expansion from being optimized? Is there any method to disable register allocate optimization? Thanks in advance. Yang

...ant to move the formal argument from the specific register class to other register class. I implement it in LowerFormalArguments() like this: .... for (auto &VA : ArgLocs) { if (VA.isRegLoc()) { // Arguments passed in registers EVT RegVT = VA.getLocVT(); VReg = RegInfo.createVirtualRegister(&FOO::BRegsRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); SDValue ArgIn_copy = DAG.getNode(FOOISD::MOVE_FLAG , dl, MVT::i32, Chain, ArgIn); // this node is added in order to move the value from BRegs class to A...

Look for createVirtualRegister. These are examples in PPCISelLowering.cpp. Evan On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > Hi Evan, > > Evan Cheng wrote: >> The patch looks great. But I do have one comment: >> >> +let usesCustomDAGSchedInserter = 1 in { >> + let Uses = [CR0] in { &gt...

...> one at > a time. <snip> > 4. The DAG scheduler pass (which creates machine instrs from dag > nodes) > currently thinks of register operands as simple unsigned's for > vreg > #'s. This needs to be extended to be vreg+subreg pairs (see > 'CreateVirtualRegisters'). > 5. We need to decide how to represent subregs in the DAG. Your > SDSubOperand idea is fine, but I don't think it needs to be an > actual > new subclass of SDOperand. Instead, it could just be a binary > SDNode, > where the LHS is the register inpu...

...second case, although there is nothing wrong with using it for the first case as well. However, in the first case we know immediately that a scratch register is necessary, so why not just ask the register allocator for one? Basically, I think storeRegToStackSlot should be allowed to call MRI->createVirtualRegister() when it needs a scratch register. That doesn't work today because the register allocators don't expect it. I don't see any fundamental problems preventing it, though. We would need to make sure that all 4 register allocators can handle it. RAFast is the most difficult to fix. /j...

Hi Evan, Evan Cheng wrote: > The patch looks great. But I do have one comment: > > +let usesCustomDAGSchedInserter = 1 in { > + let Uses = [CR0] in { > + let Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB,

...at it suddenly just changed behavior. > > It looks like to me that InstrEmitter.cpp:getVR is the one assigning the > virtual register no? > > > No, IIRC getVR only create the virtual register for implicit defs. Which > is not your case, right? > > > Though this code in CreateVirtualRegisters: > > const TargetRegisterClass *RC = > TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); > > That returns GPRBaseRegs for RC, but it then decides to constrain it based > on type: > > if (i < NumResults && TLI->isTypeLegal(Node->get...

...eamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class mytarget::ARegsRegClass unsigned ScratchReg = MF.getRegInfo().createVirtualRegister(&mytarget::ARegsRegClass); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); BuildMI(*MI.getParent(), II, dl, TII.get(mytarget::ADD_AReg), ScratchReg).addReg(FramePtr).addImm(Offset); // Update the original instruction to use the scratch register. MI.getOperand(FIOperandNum).Ch...

...DAG is constructed due to > SelectAddr().) > > SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base); > Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32); > Replying to myself here. This worked a bit better :) const unsigned addressReg = RegMap->createVirtualRegister(&M68K::AR32RegClass); SDOperand chain = CurDAG->getCopyToReg(Base, addressReg, Base); Base = CurDAG->getCopyFromReg(chain, addressReg, MVT::i32); // Andreas -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm...

...gt;> MBB_erase->addSuccessor(MBB_cond); >> MBB_erase->addSuccessor(MBB_end); >> >> MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); >> const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); >> unsigned regA = MRI.createVirtualRegister(AddrRegClass); >> unsigned regB = MRI.createVirtualRegister(AddrRegClass); >> unsigned regC = MRI.createVirtualRegister(AddrRegClass); >> >> // Set the indice >> BuildMI(*MBB, MI, db, >> TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); >...

Hi, I have a task to complete and I'm getting stuck. I can't find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I'll not go into why: That would take the discussion away from the essential problem. E.g. Replace: fmuls %f20,%f21,%f8 with the

...t;> >> It looks like to me that InstrEmitter.cpp:getVR is the one assigning the >> virtual register no? >> >> >> No, IIRC getVR only create the virtual register for implicit defs. Which >> is not your case, right? >> >> >> Though this code in CreateVirtualRegisters: >> >> const TargetRegisterClass *RC = >> TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); >> >> That returns GPRBaseRegs for RC, but it then decides to constrain it >> based on type: >> >> if (i < NumResults &&...

...amount of work to port from one version to the next though, I did not personally do the 3.4 to 3.6 porting. I agree though, it was very strange that it suddenly just changed behavior. It looks like to me that InstrEmitter.cpp:getVR is the one assigning the virtual register no? Though this code in CreateVirtualRegisters: const TargetRegisterClass *RC = TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); That returns GPRBaseRegs for RC, but it then decides to constrain it based on type: if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { const Ta...