search for: reg0

...(this code is produced by bugpoint from a bigger test-case): If you need the BC file, it is attached: # Machine code for Insert(): Live Ins: R0 in VR#1025 R1 in VR#1026 entry: 0x8fdac90, LLVM BB @0x8fc2c48, ID#0: Live Ins: %R0 %R1 %reg1026<def,dead> = MOVr %R1<kill>, 14, %reg0, %reg0 %reg1025<def> = MOVr %R0<kill>, 14, %reg0, %reg0 %reg1024<def> = MOVr %reg1025, 14, %reg0, %reg0 CMPri %reg1025<kill>, 0, 14, %reg0, %CPSR<imp-def> Bcc mbb<UnifiedReturnBlock,0x8fdad70>, 10, %CPSR<kill> Successors...

2009/1/13 Evan Cheng <echeng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > >> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >> Predecessors according to CFG: 0x8fdac90 (#0) >> %R0<def> = MOVi 0, 14, %reg0, %reg0 >> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >> [0x8fc2d68 + 0] >> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >> BX_RET 14, %reg0 &g...

On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: > Predecessors according to CFG: 0x8fdac90 (#0) > %R0<def> = MOVi 0, 14, %reg0, %reg0 > *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) > [0x8fc2d68 + 0] > %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 > %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 > BX_RET 14, %reg0 Ok, ignore my earl...

...eng <echeng at apple.com>: >>> >>> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >>> >>>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>>> Predecessors according to CFG: 0x8fdac90 (#0) >>>> %R0<def> = MOVi 0, 14, %reg0, %reg0 >>>> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >>>> [0x8fc2d68 + 0] >>>> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >>>> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >&g...

...> 2009/1/13 Evan Cheng <echeng at apple.com>: >> >> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>> Predecessors according to CFG: 0x8fdac90 (#0) >>> %R0<def> = MOVi 0, 14, %reg0, %reg0 >>> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >>> [0x8fc2d68 + 0] >>> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >>> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >>> BX...

...hould be marked with Uses = [LR] since it uses LR. However, this won't work if there is a call BL before the BX_RET. BL is marked as if it implicitly define LR. So we'll end up with this (hello world example): Live Ins: %LR %R7 %SP<def> = SUBri %SP<kill>, 8, 14, %reg0, %reg0 STR %LR<kill>, %SP, %reg0, 4, 14, %reg0 STR %R7<kill>, %SP, %reg0, 0, 14, %reg0 %R7<def> = MOVr %SP, 14, %reg0, %reg0 %R0<def> = LDR <cp#0>, %reg0, 0, 14, %reg0, Mem:LD(4,4) [<unknown> + 0] BL <ga:puts>,...

...rrently it is not the case, or? > > No, LR is not the frame pointer. It's the link register (caller address). It > should be available as a general purpose register. OK. > The bug is elsewhere. It has to do with kill / dead markers. > %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 > %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 > BX_RET 14, %reg0 > LR is restored here but it's not killed before the end of the block is > reached. Hmm. I have no idea about what ARM backend does. My register allocator just assigns the r...

...eVariables is not updated, so there may exist inconsistencies): BB2: preheader, BB3: header & latch, BB4: exit (before transformation) BB#2: derived from LLVM BB %entry.bb_crit_edge Predecessors according to CFG: BB#0 %reg1025<def> = MOVr %reg1034<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1024<def> = MOVr %reg1033<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1036<def> = MOVi 0, pred:14, pred:%reg0, opt:%reg0 %reg1038<def> = MOVr %reg1024<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1039<def> = MOVr %reg1025...

...efine LR. So we'll end up with this (hello world > example): PPC has the call (BL) marked with Defs=LR and the return (BLR) marked with Uses=LR, and works AFAIK. Let me figure out what's different... > Live Ins: %LR %R7 > %SP<def> = SUBri %SP<kill>, 8, 14, %reg0, %reg0 > STR %LR<kill>, %SP, %reg0, 4, 14, %reg0 > STR %R7<kill>, %SP, %reg0, 0, 14, %reg0 > %R7<def> = MOVr %SP, 14, %reg0, %reg0 > %R0<def> = LDR <cp#0>, %reg0, 0, 14, %reg0, Mem:LD(4,4) > [<unknown> + 0] >...

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021] (after optimization) %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0 Are there any reasons they need to be removed?...

...register allocation in llvm, using: $llc -debug test.bc where, test.c is like: int a, b, c, d, x; a = 3; b = 5; d = 4; x = 100; if ( a > b ) ...... And I got the machine code before register allocation: MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a] MOV32mi <fi#3>, 1, %reg0, 0, %reg0, 5; mem:ST4[%b] MOV32mi <fi#5>, 1, %reg0, 0, %reg0, 4; mem:ST4[%d] MOV32mi <fi#6>, 1, %reg0, 0, %reg0, 100; mem:ST4[%x] %reg16384<def> = MOV32rm <fi#3>, 1, %reg0, 0, %reg0; mem...

The following is the code fragment after "# *** IR Dump Before Prolog/Epilog Insertion & Frame Finalization ***:". * MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 0 * * MOV32mr <fi#2>, 1, %reg0, 0, %reg0, %ECX<kill>* * %EAX<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0* * MOV32mr %reg0, 1, %reg0, <ga:@one+4>, %reg0, %EAX<kill>* * %EAX<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0* * ADJCALLSTACKDOWN32 8, %ES...

...ag=true JIT gives me following debug messages: ********** Function: main Ifcvt: function (0) 'main' block 0 offset 0 size 40 block 0 offset 0 size 40 JITTing function 'main' JIT: Starting CodeGen of Function main JIT: Emitting BB0 at [0x4512e010] JIT: 0x4512e010: STM %SP, 12, 14, %reg0, %R11<kill>, %LR<kill> 0xe92d4800 JIT: 0x4512e014: %SP<def> = SUBri %SP<kill>, 8, 14, %reg0, %reg0 0xe24dd008 JIT: 0x4512e018: %R0<def> = MOVi 20, 14, %reg0, %reg0 0xe3a00014 JIT: 0x4512e01c: STR %R0<kill>, %SP, %reg0, 4, 14, %reg0, Mem:ST(4,4) [b + 0] 0x...

...two questions regarding MachineMemOperands and dependence information. > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > (before optimization) > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] > %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021] > > (after optimization) > %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0 > > Are there any re...

...I handle this case. 1: # Machine code for function test5: Frame Objects: fi#-2: size=2, align=4, fixed, at location [SP+8] fi#-1: size=2, align=8, fixed, at location [SP+4] Function Live Outs: %AX BB#0: derived from LLVM BB %entry %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390 %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390 %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391 %reg16384<def> = COPY %...

...g somewhere. The assembly code generated for the function is: BB#0: derived from LLVM BB %entry %RSP<def> = SUB64ri8 %RSP, 24, %EFLAGS<imp-def,dead>; dbg:l8.cpp:1:1 PROLOG_LABEL <MCSym=.Ltmp0>; dbg:l8.cpp:1:1 DBG_VALUE %EDI, 0, !"arg1"; dbg:l8.cpp:3:1 MOV32mi %RSP, 1, %reg0, 20, %reg0, 21; mem:ST4[%X] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 16, %reg0, 22; mem:ST4[%Y] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 12, %reg0, 23; mem:ST4[%Z] dbg:l8.cpp:1:1 %EDI<def> = MOV32rm %RSP, 1, %reg0, 20, %reg0; mem:LD4[%X] dbg:l8.cpp:1:1 MOV32mr %RSP, 1, %reg0, 12, %reg0, %EDI; mem...

...t 2800 1 at 2802 +[2808,2810:0) +[2810,2811:1) Added new interval: %reg2564,0 = [2808,2810:0)[2810,2811:1) 0 at 2808 1 at 2810 Mapped %reg2559 and folded instruction: %reg2559<def> = ADD64rr %reg2559, %reg1579, %EFLAGS<imp-def,dead> ; srcLine 0 into: ADD64mr <fi#165>, 1, %reg0, 0, %reg1579, %mreg23<imp-def,dead> ; srcLine 0 Virt folded mapped NewMI 0x9405f70: ADD64mr <fi#165>, 1, %reg0, 0, %reg1579, %mreg23<imp-def,dead> ; srcLine 0 to %reg2559 +[2820,2822:0) Added new interval: %reg2565,0 = [2820,2822:0) 0 at 2820 Mapped %reg2559 and folded...

...emOperands and dependence > information. > > > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined > and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > > > (before optimization) > > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; > mem:LD4[%uglygep10] > > %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; > mem:LD4[%uglygep2021] > > > > (after optimization) > > %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, > pred...

Hi everyone, I am trying to expand one instruction into multiple instructions on MIPS. For example, I try to expand: sh src, imm(dst) into: (1) sb src, imm(dst) (2) srl reg0, src, 8 (3) sb reg0, (imm+1)(dst) Here, reg0 are created with createVirtualRegister. However, instr(2) will not be emitted because reg0 is useless before reg0 is defined in instr(3), it is wrong! So how to prevent the expansion from being optimized? Is there any method to disable register allocate...

...from test\CodeGen\X86\xor.ll # Machine code for function test3: Frame Objects: fi#-2: size=4, align=4, fixed, at location [SP+8] fi#-1: size=4, align=8, fixed, at location [SP+4] Function Live Outs: %EAX BB#0: derived from LLVM BB %entry %reg16385<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-2] GR32:%reg16385 %reg16384<def> = MOV32rm <fi#-1>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-1] GR32:%reg16384 %reg16388<def> = MOV32ri 1; GR32:%reg16388 %reg16392<def> = XOR32ri %reg16385, 4294967294, %EFLAGS<imp-def>;...