llvm dev - Jan 2012 - [LLVMdev] TableGen: Avoid/Ignore the "no immediates on RHS of commutative node" constraint.

Dear all,

I was wondering if it is possible in TableGen to either:

1. Selectively define an instruction depending on an SDNode's properties,
e.g. if the SDNode is not commutative.
2. Override/ignore the TableGen error given when a commutative node has an
immediate on the LHS.

My case comes from trying to define a generic ALU operation multiclass for
my target, which includes a "dest_reg,immediate,src_reg" format. This
is
disallowed for commutative SDAG nodes (e.g. 'add') in LLVM, as the RHS
cannot be an immediate (I assume for optimization purposes). I think I
could achieve this with nested multiclasses, e.g.:

multiclass ALUOp<..> {
...
}

multiclass ALUOp_not_comm<..> {
  defm : ALUOp<...>;

  // Plus the 'dest_reg,immediate,src_reg' format.
}

defm ADD : ALUOp<..>
defm SUB : ALUOp_not_comm<..>


But this feels slightly dirty to me, not to mention more annoying to
maintain (since in my target's eyes there is no difference between the
formats for ADD and SUB), so I just wanted to check if there was any way to
avoid this.

Thanks,
Stephen
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