search for: multiclass

Bill, Sorry if I wasn't clear enough. I wasn't referring to multiclass's that define other classes, but with using patterns inside of a multiclass to reduce redundant code. For example: multiclass IntSubtract<SDNode node> { def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; def _i32 : P...

On Tue, Feb 10, 2009 at 8:27 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Bill, > Sorry if I wasn't clear enough. I wasn't referring to multiclass's that > define other classes, but with using patterns inside of a multiclass to > reduce redundant code. > For example: > multiclass IntSubtract<SDNode node> > { > def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), > (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPR...

...on >> this functionality with the understanding that it is desired. Please >> tell me now if we've changed our minds. > > No, I think for-loops for top-level defs could be a useful feature. Ok, we're on the same page here. > I don't want to allow for-loops inside multiclasses. The multiclasses > and for-loops provide essentially the same macro functionality with > different syntax. Mixing them would lead to a very confusing > language. Agreed about multiclasses and for loops implementing similar things. Multiclasses are implemented as a big hack in TableGe...

In TableGen, can multiclasses inherit from one another? I notice that there's a lot of redundancy in the X86 .td files that could go away with multiclass inheritance. -Dave

That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: multiclass instmcRegImm<...> { def rr: inst<...>; def ri: inst<...>; def ir: inst<...>; def ii: inst<...>; } multiclass instmc<...> { defm i8 : instmcRegImm<...>; ^-- repeat f...

...source, there are around 50 different types of instruction within each group, so reducing the repetition is quite significant. But there is a downside. For each of the above I also have variations that are a result of different processor and ISA versions, and because of this I have to use ‘multiclass/defm’ to define the descriptions along with ‘Require’ predicates. The same approach does not work with ‘multiclass/defm’ though, because TableGen does not support ‘foreach’ with ‘multiclass/defm’. I have experimented with adapting TableGen to do this, but I am just not knowledgeable enough abo...

Is there a way to define a multi-class pattern in tablegen? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale, CA. 94085 P: 408-749-3966 -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Is there a way to define a multi-class pattern in tablegen? > Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td, et al. -bw

On Mar 23, 2009, at 5:14 PM, David Greene wrote: > In TableGen, can multiclasses inherit from one another? I notice > that there's > a lot of redundancy in the X86 .td files that could go away with > multiclass > inheritance. Nope, not currently. That would be a nice feature though! -Chris

Hello all, I'm working with the svm (libsvm) implementation from library(e1071). Currently I'm trying to extend recursive feature elimination (R-SMV) to work with multiclass classification. My problem is that if I run svm for a 3 class problem I get a 2-D vector back from model$coefs, can someone explain me what this values are? I understand them in the 2-class problem where this is a 1-D vector... the help only says : coefs The corresponding coefficients times the...

...* Absolute memory location * Immediate mode o Stored in the instruction, e.g. "#400". Quite a few instructions support arbitrary choices of EA (effective addressing) modes for both operands, giving an explosion of permutations (11 * 11 !!). I thought about using a nested multiclass declaration to resolve this, as in multiclass EAPermuteRhs<dag lhs_oper, string asmstr> { def _dx : I<(outs DataRegister:$dst), lhs_oper, ..... > ; def _ax : I<(outs AddressRegister:$dst), lhs_oper, ..... > ; def _ax_postincrement : I<(outs AddressRegister:$dst), lhs_ope...

Hi, Justin > We're been writing multiclasses for each unique type of instruction. The > current PTX_LOGIC version is for 3-operand instructions. A new multiclass > needs to be created for 2-operand logic instructions. I am trying to add a multiclass for 2-operand logic instructions. For example, multiclass PTX_LOGIC_2OP<strin...

I believe multiclasses can be nested. Could that help you reduce the duplication? --Sean Silva On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amo...

...ot change anything before the 3.0 branch. But I am working on > this functionality with the understanding that it is desired. Please > tell me now if we've changed our minds. No, I think for-loops for top-level defs could be a useful feature. I don't want to allow for-loops inside multiclasses. The multiclasses and for-loops provide essentially the same macro functionality with different syntax. Mixing them would lead to a very confusing language. /jakob

Hi Jakob and David, The for-loop inside multiclass definition does not have to add extra abstraction layer. As in the pseudo codes that David wrote earlier (see below), it only condenses the repetitive 'def' statements inside the multiclass definition into a more compact and less copy-paste style form, instead of encapsulating them somewher...

Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > I think it is best if we take small steps. Small steps. Yes. > Please confirm that you have understood the message from Evan and me > that we disagree with the general direction of removing redundancy > from instruction definitions, and that your patches to that effect > will be rejected. Yes, I get it. I think I have

...ith the understanding that it is desired. Please >>> tell me now if we've changed our minds. >> >> No, I think for-loops for top-level defs could be a useful feature. > > Ok, we're on the same page here. > >> I don't want to allow for-loops inside multiclasses. The multiclasses >> and for-loops provide essentially the same macro functionality with >> different syntax. Mixing them would lead to a very confusing >> language. > > Agreed about multiclasses and for loops implementing similar things. > Multiclasses are implement...

I think a multiclass may be a better fit for what you are trying to do. In fact, this is the canonical example for multiclasses: <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>. --Sean Silva On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wro...

...t; text="#000000"> 陳韋任 wrote: <blockquote cite="mid:20110509013918.GA13760@cs.nctu.edu.tw" type="cite"> <pre wrap="">Hi, Justin </pre> <blockquote type="cite"> <pre wrap="">We're been writing multiclasses for each unique type of instruction. The current PTX_LOGIC version is for 3-operand instructions. A new multiclass needs to be created for 2-operand logic instructions. </pre> </blockquote> <pre wrap=""><!----> I am trying to add a multiclass for 2-op...

I'm trying to find examples of the foreach pattern being used in tablegen files. The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal. So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations. Instead of writing all the combinations out, I'd like to use