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2012 Jan 14
0
[LLVMdev] TableGen: Avoid/Ignore the "no immediates on RHS of commutative node" constraint.
Ivan,
Sorry, no, I wasn't clear enough. Both "op dst_reg,immediate,src_reg" and
"op dst_reg,src_reg,immediate" are allowed in the ALU ops. For most
instructions these are two different things - e.g. sub a,5,b is different
from sub,a,b,5 obviously - but for things like add they just define the
same thing.
My problem is that LLVM won't allow immediates o...
2012 Jan 14
0
[LLVMdev] TableGen: Avoid/Ignore the "no immediates on RHS of commutative node" constraint.
...ing on an SDNode's properties,
e.g. if the SDNode is not commutative.
2. Override/ignore the TableGen error given when a commutative node has an
immediate on the LHS.
My case comes from trying to define a generic ALU operation multiclass for
my target, which includes a "dest_reg,immediate,src_reg" format. This is
disallowed for commutative SDAG nodes (e.g. 'add') in LLVM, as the RHS
cannot be an immediate (I assume for optimization purposes). I think I
could achieve this with nested multiclasses, e.g.:
multiclass ALUOp<..> {
...
}
multiclass ALUOp_not_comm<..> {...