Displaying 2 results from an estimated 2 matches for "aluop_not_comm".
2012 Jan 14
0
[LLVMdev] TableGen: Avoid/Ignore the "no immediates on RHS of commutative node" constraint.
...t;dest_reg,immediate,src_reg" format. This is
disallowed for commutative SDAG nodes (e.g. 'add') in LLVM, as the RHS
cannot be an immediate (I assume for optimization purposes). I think I
could achieve this with nested multiclasses, e.g.:
multiclass ALUOp<..> {
...
}
multiclass ALUOp_not_comm<..> {
defm : ALUOp<...>;
// Plus the 'dest_reg,immediate,src_reg' format.
}
defm ADD : ALUOp<..>
defm SUB : ALUOp_not_comm<..>
But this feels slightly dirty to me, not to mention more annoying to
maintain (since in my target's eyes there is no difference...
2012 Jan 14
0
[LLVMdev] TableGen: Avoid/Ignore the "no immediates on RHS of commutative node" constraint.
...use "add" is commutative, the instruction selector will have both
> patterns to match, one with LHS as an immediate and the other one with RHS
> as an immediate.
>
> Regards,
> Ivan
>
> multiclass ALUOp<..> {
>> ...
>> }
>>
>> multiclass ALUOp_not_comm<..> {
>> defm : ALUOp<...>;
>>
>> // Plus the 'dest_reg,immediate,src_reg' format.
>> }
>>
>> defm ADD : ALUOp<..>
>> defm SUB : ALUOp_not_comm<..>
>>
>>
>> But this feels slightly dirty to me, not to me...