search for: defm

In BPF, an ADD instruction is defined as a 2 register instruction: 0x0f. add dst, src. dst += src In BPFInstrInfo.td this kind of ALU instruction is defined with: def _rr : ALU_RR<BPF_ALU64, Opc, (outs GPR:$dst), (ins GPR:$src2, GPR:$src), "$dst "#OpcodeStr#" $src", [(set

...IntRegs:$c))]>; def ri : F3_2<2, Op3Val, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), !strconcat(OpcStr, " $b, $c, $dst"), [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; } which allows it to use instructions like: defm AND : F3_12<"and" , 0b000001, and>; defm OR : F3_12<"or" , 0b000010, or>; defm XOR : F3_12<"xor" , 0b000011, xor>; defm SLL : F3_12<"sll" , 0b100101, shl>; defm SRL : F3_12<"srl" , 0b100110, srl>;...

...ere are around 50 different types of instruction within each group, so reducing the repetition is quite significant. But there is a downside. For each of the above I also have variations that are a result of different processor and ISA versions, and because of this I have to use ‘multiclass/defm’ to define the descriptions along with ‘Require’ predicates. The same approach does not work with ‘multiclass/defm’ though, because TableGen does not support ‘foreach’ with ‘multiclass/defm’. I have experimented with adapting TableGen to do this, but I am just not knowledgeable enough about ho...

On Tuesday 16 June 2009 19:35, David Greene wrote: > So which is more intuitive and less error-prone? > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, > i32i8imm, "blend", "blend", "f32", 4>; > > or > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, > i32i8imm,...

...asmstr> { def _dx : I<(outs DataRegister:$dst), lhs_oper, ..... > ; def _ax : I<(outs AddressRegister:$dst), lhs_oper, ..... > ; def _ax_postincrement : I<(outs AddressRegister:$dst), lhs_oper, ..... > ; // And many more } multiclass EAPermute<string asmstr> { defm _dx : EAPermuteRhs<(ins DataRegister:$src), asmstr> ; defm _ax : EAPermuteRhs<(ins AddressRegister:$src), asmstr> ; // etc } This would allow me to generate the complete host of permutations for say, MOVE, with the declaration: defm MOVE : EAPermute<"move"> ; Howe...

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

..._v4f32 : X86ValueType { let VT = v4f32; let RegClass = VR128; let suffix = "ps"; } class X86_v8f32 : X86ValueType { let VT = v8f32; let RegClass = VR256; let suffix = "ps"; } Ok, you get the picture. Now let's look at how we would write instruction patterns: defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, i32i8imm, "blend", "blend", "f32">; defm BLENDPD : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0D, i32i8imm, "blend", "blend&qu...

...------------------------------===// //===----------------------------------------------------------------------===// // Instruction format superclass //===----------------------------------------------------------------------===// include "DLXInstrFormats.td" // arithmetic instructions defm ADD : RegisterImmediateFormat<"add", 0b001000, add>; defm DIV : RegisterImmediateFormat<"div", 0b001001, udiv>; defm MUL : RegisterImmediateFormat<"mul", 0b001011, mul>; defm SUB : RegisterImmediateFormat<"sub", 0b001010, sub>; // log...

Hi, I'm looking at scalar and packed instructions in X86. The instruction VCOMISS is scalar. May I remove SSEPackedSingle/SSEPackedDouble domain from it? defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG; defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, "ucomisd", SSE...

...d, perhaps we should > discuss what it is supposed to look like? Don't throw the Greenspunning term around unless you really mean it. The problem I solved via multidefs was this: how does one write a set of Pat<> patterns in a generic way? For example, I want to be able to do this: defm MOVH : vs1x_fps_binary_vv_node_rmonly< 0x16, "movh", undef, 0, // rr [(undef)], // rm [(set DSTREGCLASS:$dst, (DSTTYPE (movlhps SRCREGCLASS:$src1, (DSTTYPE (bitconvert...

...t; // Match load from a relocatable address to a load with GRP: > def: Pat<(load (addr_use_grp tglobaladdr:$addr)), > (load (movimm tglobaladdr:$addr), GRP)>; > I'm not entirely sure what to replace 'load' with in the patterns above. I notice that we have these defm's in our XSTGInstrInfo.td file: defm LOADI64 : LoadOp< 0b1001010, "load", OpInfo_I64, II_LOAD1 >; defm LOADF64 : LoadOp< 0b1001010, "load", OpInfo_F64, II_LOAD1 >; defm LOADI32 : LoadOp< 0b1001010, "load", OpInfo_I32, II_LOAD1 >; defm LOADF32 : L...

The TableGen language seems to be growing Lisp macros from two different directions. Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs. It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like? /jakob

Hi, Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. Instructions are defined as follow in TableGen: defm ADD64 : ALU32<"add", 1, 1, addc>; defm ADD64C : ALU32<"addrc", 1, 2, adde>; Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly. Is there a default guarantee that nothing...

Hi, all I am trying to add "not" instruction support to PTX backend. I add the line below in PTXInstrInfo.td, defm NOT : PTX_LOGIC<"not", not>; But I get errors below, ------------------------------------------------------------------------------- Included from PTX.td:75: PTXInstrInfo.td:732:10: error: Value 'PTX_LOGIC::opnode' of type 'SDNode' is incompatible with initialize...

...er-register preload instruction for NaCl (and keep the register-immediate), and instead of my localmod being to delete the 'rs' def from multiclass APreLoad I'd like to do the cleaner thing and have rs require IsNotNaCl. This unfortunately doesn't seem to work because the subsequent defm have their own Requires. The way preloads are set up right now makes sense and I don't think they should be changed. Do I have the wrong approach in trying to add Requires<[IsNotNaCl]> to multiclass APreLoad's def rs, and expecting this to be union'ed with defm PLD/PLDW/PLI's...

Hi all, I try to run such a line in TableGen but seems it's not working. What is the problem with this code? multiclass cond { let Inst{1-0}=0b11 in defm fxy: ConditionalALU; .... } I receive this error: test.td:162:11: error: expected '=' in let expression let Inst{1-0}=0b11 in defm fxy: ConditionalALU; ^ -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/l...

...;2, Op3Val, > (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), > !strconcat(OpcStr, " $b, $c, $dst"), > [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; > } > > which allows it to use instructions like: > > defm AND : F3_12<"and" , 0b000001, and>; > defm OR : F3_12<"or" , 0b000010, or>; > defm XOR : F3_12<"xor" , 0b000011, xor>; > defm SLL : F3_12<"sll" , 0b100101, shl>; > defm SRL : F3_12<"srl" ,...

...I have a couple of questions. I am using LLVM 2.6. First, if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, defm SRA : F3_12<"mysra", 0b100111, sra>; Is this correct? When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "mysra". I looked into SparcGenAsmWriter.inc, and made sure that string AsmStrs includes "mysra"....

...in J. O'Riordan via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> But there is a downside. >> >> For each of the above I also have variations that are a result of different >> processor and ISA versions, and because of this I have to use >> ‘multiclass/defm’ to define the descriptions along with ‘Require’ >> predicates. The same approach does not work with ‘multiclass/defm’ though, >> because TableGen does not support ‘foreach’ with ‘multiclass/defm’. >> >> I have experimented with adapting TableGen to do this, but I am just n...

On Jun 16, 2009, at 5:49 PM, David Greene wrote: > On Tuesday 16 June 2009 19:35, David Greene wrote: > >> So which is more intuitive and less error-prone? >> >> defm BLENDPS : >> sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, >> i32i8imm, "blend", "blend", "f32", 4>; >> >> or >> >> defm BLENDPS : >> sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi&...