search for: aluop

...for my target, which includes a "dest_reg,immediate,src_reg" format. This is disallowed for commutative SDAG nodes (e.g. 'add') in LLVM, as the RHS cannot be an immediate (I assume for optimization purposes). I think I could achieve this with nested multiclasses, e.g.: multiclass ALUOp<..> { ... } multiclass ALUOp_not_comm<..> { defm : ALUOp<...>; // Plus the 'dest_reg,immediate,src_reg' format. } defm ADD : ALUOp<..> defm SUB : ALUOp_not_comm<..> But this feels slightly dirty to me, not to mention more annoying to maintain (since in...

...let Pattern = (set R:$dst, (add R:$src, imm:$b); > } > > Because "add" is commutative, the instruction selector will have both > patterns to match, one with LHS as an immediate and the other one with RHS > as an immediate. > > Regards, > Ivan > > multiclass ALUOp<..> { >> ... >> } >> >> multiclass ALUOp_not_comm<..> { >> defm : ALUOp<...>; >> >> // Plus the 'dest_reg,immediate,src_reg' format. >> } >> >> defm ADD : ALUOp<..> >> defm SUB : ALUOp_not_comm<...

...n backend. I'm also developing the target architecture (maybe to go in an fpga eventually) and I'm intentionally making it extremely simple. I think of it as a narrow microcode, because (for example) performing an add requires a sequence of instructions like: set aluin1 = r1 set aluin2 = r2 aluop add set r3 = aluout I've started implementing the backend in clang, and I got this basic example working by modifying my backend's implementation of SelectionDAGISel::Select to handle ISD::ADD and transform it into the above 4-instruction sequence. However, I'd like to expand the archi...