llvm dev - Jul 2011 - [LLVMdev] Sparc: handling unused operands in instruction format F3_3

Greetings,

while attempting to TableGen-ify the Sparc code generator, I've hit a
bit of a snag.

Sparc has a few well-defined instruction formats. For example, format
3 operation 3 (F3_3) is as follows:

[op][rd][op3][rs1][opf][rs2]

op = 3
rd = destination register
op3 = opcode
rs1 = source register 1
opf = opcode (floating-point)
rs2 = source register 2

So far so good. However, some operations ignore some instruction parts
(for example, FABSS aka single-precision floating absolute value
ignores rs1 because it is by nature a unary operation, and FCMPS aka
single-precision floating compare ignores rd because it only sets
flags). Sadly, this confuses TableGen, which doesn't know how to fill
the "remaining" registers, and segfaults due to complications from an
out-of-bounds array access.

How am I to handle this? I thought about creating subclasses of F3_3
(such as F3_3unary or F3_3nodest) and therein explicitly assigning
values to the ignored registers (to prevent TableGen from trying and
failing to populate them), but I don't know if this is the Right Thing
to do.

Cheers,
~~ Ondra

P. S.: For those inclined, the Sparc manual is available at
http://sparc.org/standards/V8.pdf