search for: fabss

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2016 Mar 21
2
PATCH: clang/LLVM - Sparc - inline ASM with floating pointer registers
Hi lists, Sorry for cross-posting, but these two patches are of concern to clang and llvm. I'm compiling C-code which includes inline assembler which looks like the following using the sparc-target: static inline float fabsf(float a) { float res; __asm __volatile__("fabss %1, %0;" : "=f"(res) : "f"(a)); return res; } This fails with llvm/clang - trunk/master. I patched clang and llvm and, as I'm new to both project, I'm having doubts that it is enough - however it works. What would be n...
2016 Mar 21
0
[cfe-dev] PATCH: clang/LLVM - Sparc - inline ASM with floating pointer registers
...-posting, but these two patches are of concern to clang > and llvm. > > I'm compiling C-code which includes inline assembler which looks like > the following using the sparc-target: > > static inline float fabsf(float a) > { > float res; > __asm __volatile__("fabss %1, %0;" > : "=f"(res) > : "f"(a)); > return res; > } > > This fails with llvm/clang - trunk/master. > > I patched clang and llvm and, as I'm new to both project, I'm having > doubts that it is...
2011 Jul 17
0
[LLVMdev] Sparc: handling unused operands in instruction format F3_3
...s. For example, format 3 operation 3 (F3_3) is as follows: [op][rd][op3][rs1][opf][rs2] op = 3 rd = destination register op3 = opcode rs1 = source register 1 opf = opcode (floating-point) rs2 = source register 2 So far so good. However, some operations ignore some instruction parts (for example, FABSS aka single-precision floating absolute value ignores rs1 because it is by nature a unary operation, and FCMPS aka single-precision floating compare ignores rd because it only sets flags). Sadly, this confuses TableGen, which doesn't know how to fill the "remaining" registers, and segf...
2016 Mar 22
1
[cfe-dev] PATCH: clang/LLVM - Sparc - inline ASM with floating pointer registers
...of concern to clang >> and llvm. >> >> I'm compiling C-code which includes inline assembler which looks like >> the following using the sparc-target: >> >> static inline float fabsf(float a) >> { >> float res; >> __asm __volatile__("fabss %1, %0;" >> : "=f"(res) >> : "f"(a)); >> return res; >> } >> >> This fails with llvm/clang - trunk/master. >> >> I patched clang and llvm and, as I'm new to both project, I'...
2014 Aug 08
6
[LLVMdev] Signed NaNs in APFloat arithmetic
Is there any intention of making floating absolute and negate primitive IR instructions? I ask because only a few days ago I was also faced with the task of implementing negate in my compiler, and finding no suitable IR instruction, simply subtracted from zero. But this is wrong. I could change my code to do the bit casting and fiddling, but I wonder: would that be lowered appropriately on all