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f3_1
2011 Jul 17
0
[LLVMdev] Sparc: handling unused operands in instruction format F3_3
Greetings,
while attempting to TableGen-ify the Sparc code generator, I've hit a
bit of a snag.
Sparc has a few well-defined instruction formats. For example, format
3 operation 3 (F3_3) is as follows:
[op][rd][op3][rs1][opf][rs2]
op = 3
rd = destination register
op3 = opcode
rs1 = source register 1
opf = opcode (floating-point)
rs2 = source register 2
So far so good. However, some operations ignore some instruction parts
(for example, FABSS aka single-precision floating absolu...