search for: rs2

Dear Alex, all, I was looking for fcvt.d.{w,l}{,u} in RISCVInstrInfoD and I'm not sure to understand the current definitions: 138 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> { 139 let rs2 = 0b00000; 140 } 141 142 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> { 143 let rs2 = 0b00001; 144 } 162 def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l"> { 163 let rs2 = 0b00010;...

...org> wrote: > > On 12/13/2018 6:25 AM, Alex Bradbury wrote: > > There's also likely to be cases where you want to calculate the demanded bits > > in order to determine if e.g. a W-suffixed instruction can be selected for > > `(somoeop (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))`. This is easy to match if > > the SelectionDAG contains an explicit `sext_inreg` of the result. But if not, > > you'd need to check whether the upper 32 bits are actually demanded or not. > > Could you describe more specifically where this matters? I would guess > the W...

...to work as I need to somehow tie together the fact that %Y, %ASR18 and %rd are all related to each other in the output. let Predicates = [HasLeon3, HasLeon4], Defs = [Y, ASR18], Uses = [Y, ASR18] in def SMACrr : F3_1<3, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), "smac $rs1, $rs2, $rd", [(set i32:$rd, (add i32:$asr18, (mul i32:$rs1, i32:$rs2)))] >; Perhaps a well-chosen "let Constraints=" might be used here? If so, I'm not sure I know what to put in there. I...

...t is essential to know the original type of the shift amount. The fact it was i32 means that it's safe to select SLLW in this case (as a shift amount > 31 would be undefined behaviour). It's tempting to write a pattern like the following: def : Pat<(sext_inreg (shl GPR:$rs1, GPR:$rs2), i32), (SLLW GPR:$rs1, GPR:$rs2)>; But as Eli Friedman kindly pointed out, the `sext_inreg` node can be generated in cases other than i32 to i64 widening. e.g. define i64 @tricky_shl(i64 %a, i64 %b) { %1 = shl i64 %a, %b %2 = shl i64 %1, 32 %3 = ashr i64 %2...

...higher level construct? I'd expect the former would be entirely sufficient, in which case this should be sufficient: let Predicates = [HasLeon3, HasLeon4], Defs = [Y, ASR18], Uses = [Y, ASR18] in def SMACrr : F3_1<3, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), "smac $rs1, $rs2, $rd", []>; If you want the latter, I'm not sure how you'd go about being able to pattern-match it, because of the unusual 40 bit accumulate input and output, and the unusual for sparc 16-bit inputs. Hopefully you don't...

...ulated data in the check suite are no longer the same as before parallelization was added. This seems to be due to 'parallel' changing '.Random.seed' when loading its name space: > set.seed(1) > rs1 <- .Random.seed > rnorm(1) [1] -0.6264538 > set.seed(1) > rs2 <- .Random.seed > identical(rs1, rs2) [1] TRUE > loadNamespace("parallel") <environment: namespace:parallel> > rs3 <- .Random.seed > identical(rs1, rs3) [1] FALSE > rnorm(1) [1] -0.3262334 > set.seed(1) > rs4 <- .Random.seed > identical(rs1,...

Hi Guys, Here is the setup. LVS NAT cluster with director (dir), backup director (bdir), and two realservers (rs1 and rs2) running apache webserver. SSH DSA key-based authentication set up between rs1 and rs2 in order to facilitate automated (via cron) mirorring of htdocs directories. All works fine untill I decide to host DNS on the same cluster. As soon as I start BIND on rs1, ssh no longer works to this machine. It...

Hi Im trying to add RISC V Store Instruction for an Experiment on my Target. The thing is, llvm Store Format gets Register and Pointer Type Operand. beside this, RISC-V Store Instruction takes source Register, Base Register and offset immediate type. So this takes 3 leafs. In this case, should I make new SelectionDAG Node in this case? or use BuildMI Instruction to add new Register? P.S.

...e routines:EVP_EncryptUpdate:invalid operation tincd[8324]: Error while decrypting metadata from fairfield_gw (yy.yy.yy.yy port 655) tincd[8324]: Error while decrypting: error:060A7094:digital envelope routines:EVP_EncryptUpdate:invalid operation tincd[8324]: Error while decrypting metadata from rs2 (abc::def port 655) tincd[8324]: Error while decrypting: error:060A7094:digital envelope routines:EVP_EncryptUpdate:invalid operation tincd[8324]: Error while decrypting metadata from rs2 (xx.xx.xx.xx port 655) tincd[8324]: Error while decrypting: error:060A7094:digital envelope routines:EVP_Encr...

My data looks like this: > data name G_hat_0_0 G_hat_1_0 G_hat_2_0 G_0 G_hat_0_1 G_hat_1_1 G_hat_2_1 G_1 1 rs0 0.488000 0.448625 0.063375 1 0.480875 0.454500 0.064625 1 2 rs1 0.002375 0.955375 0.042250 1 0.000000 0.062875 0.937125 2 3 rs2 0.050375 0.835875 0.113750 1 0.877250 0.115875 0.006875 0 4 rs3 0.000000 0.074750 0.925250 2 0.897750 0.102000 0.000250 0 5 rs4 0.000125 0.052375 0.947500 2 0.261500 0.724125 0.014375 1 6 rs5 0.003750 0.092125 0.904125 2 0.023000 0.738125 0.238875 1 And m...

Hello everyone, I wanted to attach a node without affecting the present nodes in any way. I tried to use MVT::Glue for that but I think I'm missing something as I could not achieve the below state. LUI LUI | | ADDI ----GLUE---- ADDI | store I've few question about this and Glue node in general, I'll be happy to get some help on

Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc" If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I do see definitions for tokens like "set", "add", ... coming from include/llvm/Targe...

Greetings, while attempting to TableGen-ify the Sparc code generator, I've hit a bit of a snag. Sparc has a few well-defined instruction formats. For example, format 3 operation 3 (F3_3) is as follows: [op][rd][op3][rs1][opf][rs2] op = 3 rd = destination register op3 = opcode rs1 = source register 1 opf = opcode (floating-point) rs2 = source register 2 So far so good. However, some operations ignore some instruction parts (for example, FABSS aka single-precision floating absolute value ignores rs1 because it is by nature...

...a front-end to provide high level optimization. We'd like to know if there's a good way to go about producing this assembly language directly. The problem I'm looking at is that one instruction can control multiple individual effects. For example, the instruction " M[ALUR2] = sw RS2; RS2 = r[20]; ALUR2 = ALUR2 add SE" does a store, a register read, and an ALU operation (keeping intermediate values in internal registers). We have encoding restrictions that allow us to fit such a group of effects into a 32 bit instruction. What would be the best way to accomplish this cod...

Hi, ABCRegister.td : def SGPR32 : RegisterClass<"ABC", [i32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; ===== Instruction selection ends: ... t8: i32 = ADDrr t37, t32

in llvm-3.6.2.src 1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file, let TwoOperandAliasConstraint = "$dst = $rs1" in { } I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction, the question is what am I doing wrong ? 2. I've noticed that TwoOperandAliasConstraint

Hi, I'm not sure. But in your lowered DAG the chain nodes are the first operands for you custom nodes, however for the other nodes the chain is the last operand. I seem to remember that during targetlowering the chain is the first operand and then it seems to switch over after ISelDAG, this confused me and may have something to do with the issue that you are seeing. I really don't

...> On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > If I have a pattern in my dot-td-file like this > > [(set i32:$dst (add i32:$rs1, i32:$rs2))] > > The question is where does the token “i32” come from, > I don’t see any definitions for i1, i8, i16, i32, … in > include/llvm/Target/*.td > > while I do see definitions for tokens like “set”, “add”, … > coming from > include/llvm/T...

...ay 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token “i32” come from, I don’t see any definitions for i1, i8, i16, i32, … in include/llvm/Target/*.td while I do see definitions for tokens like “set”, “add”, … coming from include/llvm/Target/TargetSelectionDAG.td presumably th...

...Peter via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > If I have a pattern in my dot-td-file like this > > [(set i32:$dst (add i32:$rs1, i32:$rs2))] > > The question is where does the token “i32” come from, > I don’t see any definitions for i1, i8, i16, i32, … in > include/llvm/Target/*.td > > while I do see definitions for tokens like “set”, “add”, … > coming from > include/llvm/T...