Leslie Zhai via llvm-dev
2017-Dec-21 05:03 UTC
[llvm-dev] How to implement lowerReturn for poring GlobalISel to RISCV?
Hi LLVM developers,
Thank Daniel Sanders, Aditya Nandakumar and Justin Bogner's Tutorial[1]:
Head First into GlobalISel about how to port, and Aditya took BPF target
as a simple instance:
bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, unsigned VReg) const {
assert(!Val == !VReg && "Return value without a vreg");
MIRBuilder.buildInstr(BPF::RET);
return true;
}
But how to implement it for RISCV target?
https://github.com/xiangzhai/llvm/commit/c49146edbbf655e97727e22e4a87a020fb8da6e5
Because there are separate trap return instructions[2] per privilege
level: MRET, SRET, and URET. MRET is always provided, while SRET must be
provided if supervisor mode is supported. URET is only provided if
user-mode traps are supported. and David added RISCV privileged
instructionsit[3], then merged into upstream, it might be more complex
than ARM[4] please give me some hint, thanks a lot!
[1] http://llvm.org/devmtg/2017-10/#tutorial2
[2]
https://github.com/riscv/riscv-isa-manual/blob/master/src/machine.tex#L539
[3] https://reviews.llvm.org/D40383
[4]
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMCallLowering.cpp#L280
--
Regards,
Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/
Friedman, Eli via llvm-dev
2017-Dec-21 18:53 UTC
[llvm-dev] How to implement lowerReturn for poring GlobalISel to RISCV?
On 12/20/2017 9:03 PM, Leslie Zhai via llvm-dev wrote:> Because there are separate trap return instructions[2] per privilege > level: MRET, SRET, and URET. MRET is always provided, while SRET must > be provided if supervisor mode is supported. URET is only provided if > user-mode traps are supported. and David added RISCV privileged > instructionsit[3], then merged into upstream, it might be more complex > than ARM[4] please give me some hint, thanks a lot! >lowerReturn corresponds to the LLVM IR "ret" instruction, which is always a normal function return (JALR), not a return from an interrupt. -Eli -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Leslie Zhai via llvm-dev
2017-Dec-22 00:02 UTC
[llvm-dev] How to implement lowerReturn for poring GlobalISel to RISCV?
在 2017年12月22日 02:53, Friedman, Eli 写道:> On 12/20/2017 9:03 PM, Leslie Zhai via llvm-dev wrote: >> Because there are separate trap return instructions[2] per privilege >> level: MRET, SRET, and URET. MRET is always provided, while SRET must >> be provided if supervisor mode is supported. URET is only provided if >> user-mode traps are supported. and David added RISCV privileged >> instructionsit[3], then merged into upstream, it might be more >> complex than ARM[4] please give me some hint, thanks a lot! >> > > lowerReturn corresponds to the LLVM IR "ret" instruction, which is > always a normal function return (JALR), not a return from an interrupt.Already fixed https://github.com/xiangzhai/llvm/commit/0adf9aa558dd452f8e5bffa3f5b127c58f9d3a43 but thank you to point out my fault!> > -Eli >-- Regards, Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/