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instructionset
2017 Dec 21
2
How to implement lowerReturn for poring GlobalISel to RISCV?
...7e22e4a87a020fb8da6e5
Because there are separate trap return instructions[2] per privilege
level: MRET, SRET, and URET. MRET is always provided, while SRET must be
provided if supervisor mode is supported. URET is only provided if
user-mode traps are supported. and David added RISCV privileged
instructionsit[3], then merged into upstream, it might be more complex
than ARM[4] please give me some hint, thanks a lot!
[1] http://llvm.org/devmtg/2017-10/#tutorial2
[2]
https://github.com/riscv/riscv-isa-manual/blob/master/src/machine.tex#L539
[3] https://reviews.llvm.org/D40383
[4]
https://github.com/...