| Thursday November 30 2017 |
| Time | Replies | Subject |
|---|
| 8:14PM |
0 |
Call for Speakers for the second LLVM Performance Workshop at CGO 2018 |
| 8:12PM |
2 |
PPC64 Disassembler |
| 8:02PM |
1 |
How to count instructions in a function? |
| 6:39PM |
0 |
TwoAddressInstructionPass bug? |
| 5:33PM |
0 |
How to count instructions in a function? |
| 5:08PM |
0 |
discrepancy between include/llvm/ADT/Triple.h and lib/Target/ARM/ARMGenSubtargetInfo.inc? |
| 3:51PM |
0 |
Adding MPX Intrinsics to X86 codegen |
| 3:09PM |
0 |
PPC64 Disassembler |
| 1:56PM |
1 |
overloading single argument intrinsics |
| 12:04PM |
2 |
TwoAddressInstructionPass bug? |
| 11:11AM |
1 |
SystemZ intrinsics definitions / memory flags |
| 10:38AM |
0 |
getCacheSize() implementation (retrieving subtarget id) |
| 9:56AM |
3 |
Question about visibility analysis for whole program devirtualization pass |
| 9:53AM |
2 |
PPC64 Disassembler |
| 4:20AM |
0 |
libclang API to access static array initializer |
| 1:30AM |
0 |
PPC64 Disassembler |
| 12:42AM |
2 |
Publication: Counterexample-Guided Bit-Precision Selection |
| 12:19AM |
9 |
5.0.1-rc2 has been tagged |
| |
| Wednesday November 29 2017 |
| Time | Replies | Subject |
|---|
| 9:02PM |
2 |
How to count instructions in a function? |
| 6:48PM |
3 |
PPC64 Disassembler |
| 6:08PM |
1 |
CFG normalization: avoiding `br i1 false` |
| 5:50PM |
0 |
Ensuring that dead allocations from a custom allocator are killed by LLVM |
| 5:48PM |
3 |
CFG normalization: avoiding `br i1 false` |
| 5:25PM |
0 |
Version of LLVM used in Xcode 9.1 |
| 4:23PM |
0 |
LLVM buildmaster is back to work now but two builders remain OFF |
| 2:50PM |
3 |
Version of LLVM used in Xcode 9.1 |
| 2:05PM |
1 |
CUDA kernel call with template parameters not appearing in Clang AST |
| 1:21PM |
3 |
question: access IR class Instruction from DAG SDValue |
| 12:58PM |
0 |
[RFC] Making .eh_frame more linker-friendly |
| 10:23AM |
1 |
Do I need to implement CCAssignFnForCall for porting GlobalISel to AVR target? |
| 9:23AM |
3 |
RFC: Adding 'no-overflow' keyword to 'sdiv'\'udiv' instructions |
| 8:42AM |
2 |
[RFC] Making .eh_frame more linker-friendly |
| 5:31AM |
0 |
ABI Breaking Checks |
| 4:00AM |
0 |
Do I need to implement CCAssignFnForCall for porting GlobalISel to AVR target? |
| 2:16AM |
0 |
[RFC] Making .eh_frame more linker-friendly |
| 1:35AM |
0 |
CodeExtractor buggy? |
| 1:26AM |
4 |
CodeExtractor buggy? |
| |
| Tuesday November 28 2017 |
| Time | Replies | Subject |
|---|
| 11:55PM |
1 |
Expose aliasing information in getModRefInfo (or viceversa?) |
| 10:35PM |
2 |
ABI Breaking Checks |
| 10:13PM |
2 |
LLVM buildmaster is back to work now but two builders remain OFF |
| 8:12PM |
1 |
TargetSelect.h and layering |
| 7:27PM |
2 |
TargetSelect.h and layering |
| 7:23PM |
0 |
TargetSelect.h and layering |
| 7:15PM |
2 |
TargetSelect.h and layering |
| 7:09PM |
0 |
LLVM buildmaster will be restarted in few minutes |
| 6:56PM |
0 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 5:46PM |
2 |
[LLD] Slow callstacks in gdb |
| 5:21PM |
1 |
CUDA kernel call with template parameters not appearing in Clang AST |
| 5:05PM |
2 |
Publication LLVM Related Publications Submission |
| 4:09PM |
2 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 3:29PM |
0 |
buildmaster broken? |
| 2:40PM |
0 |
[LLD] Slow callstacks in gdb |
| 8:55AM |
1 |
Go Tsan check failure |
| 8:47AM |
0 |
Go Tsan check failure |
| 8:34AM |
0 |
Changing only the opcode of a SelectionDAG node |
| 8:18AM |
1 |
Lowering operations using tablegen |
| 8:04AM |
3 |
Compilation issue "unsupported relocation on symbol" with clang 3.7.1 |
| 6:27AM |
2 |
Go Tsan check failure |
| 2:57AM |
0 |
storing MBB MCSymbol in custom section |
| 2:00AM |
2 |
variadic functions on X86_64 should (conditionally) save XMM regs even if -no-implicit-float |
| 1:28AM |
3 |
storing MBB MCSymbol in custom section |
| |
| Monday November 27 2017 |
| Time | Replies | Subject |
|---|
| 11:21PM |
0 |
Retrieving DbgInfoIntrinsics for a given value |
| 11:16PM |
0 |
Go Tsan check failure |
| 10:36PM |
0 |
LLVM Weekly - #204, Nov 27th 2017 |
| 9:24PM |
0 |
Combining install-distribution with binary stripping |
| 8:12PM |
0 |
clarification needed for the constrained fp implementation. |
| 7:22PM |
0 |
Reaching definitions on Machine IR post register allocation |
| 6:25PM |
0 |
[RFC] Enable Partial Inliner by default |
| 6:18PM |
0 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 5:50PM |
2 |
[LLD] Slow callstacks in gdb |
| 5:44PM |
2 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 5:22PM |
1 |
Is it ok to allocate > half of address space? |
| 5:02PM |
2 |
[cfe-dev] [Proposal] Automatically Cc: cfe-commits@ on Clang reviews |
| 5:00PM |
0 |
[cfe-dev] [Proposal] Automatically Cc: cfe-commits@ on Clang reviews |
| 4:42PM |
2 |
[cfe-dev] [Proposal] Automatically Cc: cfe-commits@ on Clang reviews |
| 4:31PM |
0 |
llvm compile too much memory when i userd global array |
| 4:28PM |
0 |
[LLD] Slow callstacks in gdb |
| 4:12PM |
1 |
mischeduler (pre-RA) experiments |
| 3:00PM |
3 |
[LLD] Slow callstacks in gdb |
| 2:15PM |
1 |
question about xray tls data initialization |
| 1:01PM |
0 |
question: access IR class Instruction from DAG SDValue |
| 12:56PM |
2 |
Go Tsan check failure |
| 12:51PM |
2 |
question: access IR class Instruction from DAG SDValue |
| 12:16PM |
0 |
Deadline extension: [CFP] LLVM toolchain devroom CFP at FOSDEM 2018 |
| 11:52AM |
0 |
Get values from a given type |
| 11:33AM |
1 |
Empty TokenIdentifier and multiple patterns for an instruction |
| 11:02AM |
0 |
Compilation issue "unsupported relocation on symbol" with clang 3.7.1 |
| 8:54AM |
2 |
llvm compile too much memory when i userd global array |
| |
| Sunday November 26 2017 |
| Time | Replies | Subject |
|---|
| 8:18PM |
0 |
Need some help over here |
| 6:19PM |
0 |
[cfe-dev] [Proposal] Automatically Cc: cfe-commits@ on Clang reviews |
| 4:30PM |
1 |
Remotely launching a new process with LLDB |
| 3:02PM |
0 |
question: access IR class Instruction from DAG SDValue |
| 12:09PM |
5 |
Compilation issue "unsupported relocation on symbol" with clang 3.7.1 |
| 12:58AM |
3 |
question: access IR class Instruction from DAG SDValue |
| |
| Saturday November 25 2017 |
| Time | Replies | Subject |
|---|
| 11:46PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 6:10PM |
0 |
mischeduler (pre-RA) experiments |
| 11:33AM |
0 |
Support for VS2017? |
| 10:08AM |
1 |
Runtime library components licensing / MIT License / credit requirements |
| 2:00AM |
2 |
mischeduler (pre-RA) experiments |
| |
| Friday November 24 2017 |
| Time | Replies | Subject |
|---|
| 9:25PM |
1 |
Need some help over here |
| 8:58PM |
0 |
mischeduler (pre-RA) experiments |
| 7:46PM |
0 |
LLVM Social Berlin: Auto-tuning Compiler Transformations with Machine Learning |
| 3:06PM |
3 |
Get values from a given type |
| 11:34AM |
0 |
Detecting invalid functions of template specialisations |
| 9:21AM |
2 |
Reaching definitions on Machine IR post register allocation |
| 12:22AM |
0 |
question about xray tls data initialization |
| |
| Thursday November 23 2017 |
| Time | Replies | Subject |
|---|
| 9:15PM |
1 |
JIT and atexit crash |
| 8:03PM |
1 |
[SCEV][ScalarEvolution] SE limitation impacting LV |
| 6:49PM |
2 |
JIT and atexit crash |
| 3:16PM |
4 |
[RFC] Making .eh_frame more linker-friendly |
| 12:34PM |
2 |
question about xray tls data initialization |
| 10:53AM |
3 |
mischeduler (pre-RA) experiments |
| 9:43AM |
2 |
[cfe-dev] [Proposal] Automatically Cc: cfe-commits@ on Clang reviews |
| 9:38AM |
0 |
RISC-V LLVM sync-up conference calls |
| 12:31AM |
0 |
RFC phantom memory intrinsic |
| 12:23AM |
0 |
[SCEV][ScalarEvolution] SE limitation impacting LV |
| |
| Wednesday November 22 2017 |
| Time | Replies | Subject |
|---|
| 11:58PM |
0 |
[cfe-dev] [Proposal] Automatically Cc: cfe-commits@ on Clang reviews |
| 11:43PM |
2 |
[SCEV][ScalarEvolution] SE limitation impacting LV |
| 11:05PM |
0 |
Expose aliasing information in getModRefInfo (or viceversa?) |
| 10:58PM |
0 |
[SCEV][ScalarEvolution] SE limitation impacting LV |
| 10:05PM |
0 |
LLVM Compiler Team growth |
| 9:29PM |
2 |
Retrieving DbgInfoIntrinsics for a given value |
| 7:00PM |
0 |
5.0.1 Release Update |
| 6:26PM |
0 |
[cfe-dev] Cambridge LLVM Social, Nov 22nd |
| 4:23PM |
2 |
[cfe-dev] [Proposal] Automatically Cc: cfe-commits@ on Clang reviews |
| 1:44PM |
0 |
[RFC] Making .eh_frame more linker-friendly |
| 9:01AM |
2 |
SPEC CPU2017 score using LLVM-based AOCC |
| 8:10AM |
0 |
[JIT] LLVM or Clang - strange behavior |
| 7:01AM |
0 |
Error cloning function from another module and setting it alwaysinline on custom pass |
| 5:29AM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 3:32AM |
2 |
Combining install-distribution with binary stripping |
| 3:25AM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 3:04AM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 3:03AM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 2:37AM |
0 |
question about xray tls data initialization |
| |
| Tuesday November 21 2017 |
| Time | Replies | Subject |
|---|
| 7:32PM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 5:59PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 4:23PM |
0 |
RFC MachineLICM to hoist invariant stores |
| 3:59PM |
1 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 3:32PM |
2 |
question about xray tls data initialization |
| 3:27PM |
2 |
Cambridge LLVM Social, Nov 22nd |
| 1:40PM |
0 |
Debugging LLVM IR - Reviving the DebugIR pass |
| 1:20PM |
0 |
JIT and atexit crash |
| 11:46AM |
0 |
question about xray tls data initialization |
| 10:27AM |
1 |
Meaning of loads/stores marked both atomic and volatile |
| 10:13AM |
2 |
JIT and atexit crash |
| 9:02AM |
0 |
[CFP] LLVM toolchain devroom CFP at FOSDEM 2018 |
| 8:41AM |
2 |
[RFC] Making .eh_frame more linker-friendly |
| 7:53AM |
0 |
Meaning of loads/stores marked both atomic and volatile |
| 7:51AM |
0 |
[RFC] Making .eh_frame more linker-friendly |
| 1:44AM |
0 |
Nowaday Scalar Evolution's Problem. |
| |
| Monday November 20 2017 |
| Time | Replies | Subject |
|---|
| 10:57PM |
0 |
Debugging LLVM IR - Reviving the DebugIR pass |
| 9:22PM |
1 |
Meaning of loads/stores marked both atomic and volatile |
| 9:17PM |
2 |
Meaning of loads/stores marked both atomic and volatile |
| 9:01PM |
0 |
RFC: Replace usage of Alias Set Tracker with MemorySSA in LICM |
| 8:46PM |
0 |
LLVM Weekly - #203, Nov 20th 2017 |
| 8:44PM |
0 |
Meaning of loads/stores marked both atomic and volatile |
| 7:14PM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 4:36PM |
1 |
Signed or unsigned EQ/NEQ |
| 3:56PM |
3 |
[RFC] Making .eh_frame more linker-friendly |
| 3:41PM |
0 |
Meaning of loads/stores marked both atomic and volatile |
| 3:25PM |
4 |
Meaning of loads/stores marked both atomic and volatile |
| 12:10PM |
0 |
Is llvm capable of doing loop interchange optimization? |
| 11:31AM |
1 |
Expanding SDNodes |
| 11:06AM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 10:32AM |
4 |
Debugging LLVM IR - Reviving the DebugIR pass |
| 9:43AM |
1 |
Notice: The buildbot bb.pgr.jp will be suspended within a few days |
| 4:57AM |
2 |
Nowaday Scalar Evolution's Problem. |
| 12:04AM |
0 |
JIT and atexit crash |
| |
| Sunday November 19 2017 |
| Time | Replies | Subject |
|---|
| 11:22PM |
2 |
JIT and atexit crash |
| 12:13PM |
1 |
How and where optimizing of undefined behavior happens |
| |
| Saturday November 18 2017 |
| Time | Replies | Subject |
|---|
| 10:30PM |
0 |
Job: Clang Release Manager at Apple |
| 8:55PM |
0 |
How and where optimizing of undefined behavior happens |
| 6:35PM |
2 |
How and where optimizing of undefined behavior happens |
| 5:08PM |
0 |
Problem with building Clang and LLVM using Xcode |
| 3:26PM |
2 |
Is llvm capable of doing loop interchange optimization? |
| 1:28PM |
0 |
Signed or unsigned EQ/NEQ |
| 10:53AM |
0 |
Problem with building Clang and LLVM using Xcode |
| 10:22AM |
0 |
Signed or unsigned EQ/NEQ |
| 4:50AM |
0 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 12:41AM |
2 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| |
| Friday November 17 2017 |
| Time | Replies | Subject |
|---|
| 9:51PM |
1 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 9:38PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 9:11PM |
4 |
Signed or unsigned EQ/NEQ |
| 7:15PM |
2 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 6:10PM |
0 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 5:27PM |
2 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 4:17PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 3:44PM |
1 |
X86 llvm.frameaddress/returnaddress |
| 1:17PM |
2 |
Ensuring that dead allocations from a custom allocator are killed by LLVM |
| 8:13AM |
0 |
Propagating noalias annotation |
| 8:07AM |
2 |
Propagating noalias annotation |
| 8:01AM |
0 |
Propagating noalias annotation |
| 7:55AM |
3 |
Propagating noalias annotation |
| 7:49AM |
0 |
Propagating noalias annotation |
| 7:43AM |
1 |
How does LLVM map source lines to machine instructions? |
| 7:21AM |
2 |
Propagating noalias annotation |
| 1:06AM |
0 |
Declined: RISC-V LLVM sync-up conference call |
| |
| Thursday November 16 2017 |
| Time | Replies | Subject |
|---|
| 11:47PM |
2 |
Collecting address ranges in DWARFUnit::collectAddressRanges. |
| 10:31PM |
2 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 8:20PM |
0 |
Collecting address ranges in DWARFUnit::collectAddressRanges. |
| 7:44PM |
3 |
Collecting address ranges in DWARFUnit::collectAddressRanges. |
| 7:34PM |
0 |
Declined: RISC-V LLVM sync-up conference call |
| 7:27PM |
0 |
RISC-V LLVM sync-up conference call |
| 6:03PM |
0 |
Collecting address ranges in DWARFUnit::collectAddressRanges. |
| 6:00PM |
0 |
About mismatching calling conventions |
| 4:11PM |
0 |
Propagating noalias annotation |
| 1:44PM |
2 |
question about xray tls data initialization |
| 12:14PM |
0 |
[Release-testers] 5.0.1-rc1 has been tagged |
| 9:20AM |
1 |
Looking for tests for class ARMConstantIslands |
| 8:35AM |
2 |
About mismatching calling conventions |
| 7:45AM |
0 |
Correctly linking against libLLVM (single shared library build) |
| 7:34AM |
2 |
Correctly linking against libLLVM (single shared library build) |
| 1:50AM |
0 |
[lld] Flavour option purpose |
| 1:06AM |
2 |
[lld] Flavour option purpose |
| |
| Wednesday November 15 2017 |
| Time | Replies | Subject |
|---|
| 10:17PM |
0 |
RFC MachineLICM to hoist invariant stores |
| 9:51PM |
0 |
getting nowhere with thinLTO |
| 9:08PM |
1 |
Elves, Orcs, and the Memory Growth |
| 7:13PM |
1 |
Vectorizing "hybrid" SOA |
| 6:03PM |
0 |
CFG normalization: avoiding `br i1 false` |
| 5:36PM |
0 |
RFC: Adding a JSON library to LLVM Support |
| 3:53PM |
2 |
Collecting address ranges in DWARFUnit::collectAddressRanges. |
| 3:36PM |
1 |
workaround for debug info bug? |
| 3:07PM |
0 |
Reminder: Today is the deadline for 5.0.1 Merge Requests |
| 2:29PM |
0 |
workaround for debug info bug? |
| 1:45PM |
0 |
[lld] Flavour option purpose |
| 1:24PM |
0 |
Pass Divergence Analysis data to selection DAG to drive divergence dependent instruction selection |
| 1:15PM |
2 |
CFG normalization: avoiding `br i1 false` |
| 11:10AM |
0 |
答复: hi, Is there any solution about how to add some dwarf info to the IR bitcode file. |
| 8:00AM |
2 |
workaround for debug info bug? |
| 6:26AM |
2 |
答复: hi, Is there any solution about how to add some dwarf info to the IR bitcode file. |
| 5:20AM |
0 |
workaround for debug info bug? |
| 4:51AM |
0 |
hi, Is there any solution about how to add some dwarf info to the IR bitcode file. |
| 4:47AM |
2 |
workaround for debug info bug? |
| 3:32AM |
2 |
hi, Is there any solution about how to add some dwarf info to the IR bitcode file. |
| 1:34AM |
2 |
Propagating noalias annotation |
| 1:33AM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 12:31AM |
0 |
ORC JIT and multithreading |
| |
| Tuesday November 14 2017 |
| Time | Replies | Subject |
|---|
| 11:11PM |
6 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 10:22PM |
0 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 9:40PM |
0 |
[RFC] Enable Partial Inliner by default |
| 9:15PM |
1 |
OrcJIT + CUDA Prototype for Cling |
| 6:58PM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 6:10PM |
2 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 5:29PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 5:26PM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 5:16PM |
2 |
[SCEV][ScalarEvolution] SE limitation impacting LV |
| 4:22PM |
1 |
New LLVM License |
| 4:03PM |
4 |
RISC-V LLVM sync-up conference calls |
| 3:17PM |
2 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 2:55PM |
0 |
PSA+discussion: guessInstructionProperties=0 is now usable |
| 2:38PM |
0 |
Internship @ CEA Grenoble - France: Integrity and Confidentiality of Programs and Data for Embedded Systems |
| 10:27AM |
2 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 8:39AM |
1 |
Experiment on how to improve our temporary file handing. |
| 8:10AM |
0 |
[Help]Is there any information or examples about how to build the application with llvm api?（about how to preprocess, compile , opt) |
| 3:24AM |
0 |
Reaching definitions on Machine IR post register allocation |
| 2:58AM |
1 |
Update control flow graph when splitting a machine basic block? |
| 2:07AM |
2 |
[lld] Flavour option purpose |
| 12:44AM |
3 |
PSA: debuginfo-tests workflow changing slightly |
| 12:43AM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 12:38AM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 12:38AM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 12:30AM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 12:26AM |
0 |
Correctly linking against libLLVM (single shared library build) |
| |
| Monday November 13 2017 |
| Time | Replies | Subject |
|---|
| 11:54PM |
2 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 11:49PM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 11:30PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 11:29PM |
0 |
Experiment on how to improve our temporary file handing. |
| 11:28PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 11:25PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 11:21PM |
3 |
PSA: debuginfo-tests workflow changing slightly |
| 11:19PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 11:17PM |
2 |
Experiment on how to improve our temporary file handing. |
| 11:17PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 10:15PM |
3 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 9:46PM |
0 |
Experiment on how to improve our temporary file handing. |
| 9:02PM |
0 |
LLVM Weekly - #202, Nov 13th 2017 |
| 8:37PM |
0 |
Update control flow graph when splitting a machine basic block? |
| 7:53PM |
0 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 7:48PM |
2 |
Experiment on how to improve our temporary file handing. |
| 7:25PM |
0 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 7:03PM |
0 |
Experiment on how to improve our temporary file handing. |
| 6:26PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 5:10PM |
3 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 4:09PM |
2 |
Reaching definitions on Machine IR post register allocation |
| 2:47PM |
2 |
[RFC] Enable Partial Inliner by default |
| 2:27PM |
0 |
How to objcopy via LLVM toolchain for armv7e-m ELF32LE? |
| 12:31PM |
0 |
[lld] Flavour option purpose |
| 9:06AM |
0 |
Experiment on how to improve our temporary file handing. |
| 6:14AM |
0 |
How to objcopy via LLVM toolchain for armv7e-m ELF32LE? |
| 3:32AM |
4 |
How to objcopy via LLVM toolchain for armv7e-m ELF32LE? |
| |
| Sunday November 12 2017 |
| Time | Replies | Subject |
|---|
| 8:55PM |
1 |
Intrinsic::x86_avx2_vperm2i128 |
| 6:05AM |
0 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 5:31AM |
0 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 4:52AM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 3:52AM |
2 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| |
| Saturday November 11 2017 |
| Time | Replies | Subject |
|---|
| 7:07PM |
0 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 7:06PM |
2 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 7:03PM |
2 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 6:47PM |
0 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 6:44PM |
0 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 6:42PM |
0 |
New LLVM License |
| 5:21PM |
0 |
[RFC] Enable Partial Inliner by default |
| 4:25PM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 8:20AM |
2 |
Update control flow graph when splitting a machine basic block? |
| 3:54AM |
5 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 2:57AM |
0 |
Update control flow graph when splitting a machine basic block? |
| 2:00AM |
2 |
Update control flow graph when splitting a machine basic block? |
| 1:54AM |
2 |
[Help]Is there any information or examples about how to build the application with llvm api?（about how to preprocess, compile , opt) |
| 1:35AM |
1 |
Using C++14 code in LLVM |
| 1:04AM |
2 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| |
| Friday November 10 2017 |
| Time | Replies | Subject |
|---|
| 11:14PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 11:08PM |
0 |
Get basic-block cycle cost from LLVM |
| 10:51PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 10:50PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 10:49PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 10:32PM |
0 |
LLVM buildmaster will be unavailable for a short time today |
| 10:04PM |
2 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 9:35PM |
1 |
Experiment on how to improve our temporary file handing. |
| 9:28PM |
5 |
[RFC] Enable Partial Inliner by default |
| 9:24PM |
2 |
unable to vectorize copy statement |
| 9:00PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 8:34PM |
2 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 8:00PM |
0 |
[GlobalISel] [X86] unable to legalize instruction |
| 7:02PM |
0 |
Update control flow graph when splitting a machine basic block? |
| 6:19PM |
0 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 5:12PM |
5 |
RFC: [GlobalISel] Towards a generic MI combiner framework |
| 5:12PM |
2 |
getting nowhere with thinLTO |
| 4:21PM |
0 |
Experiment on how to improve our temporary file handing. |
| 4:08PM |
0 |
[RFC] Enable Partial Inliner by default |
| 3:44PM |
0 |
Compiling LLC into one huge binary |
| 3:39PM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 2:23PM |
0 |
[RFC] Making .eh_frame more linker-friendly |
| 1:27PM |
2 |
[RFC] Making .eh_frame more linker-friendly |
| 12:52PM |
0 |
Reaching definitions on Machine IR post register allocation |
| 12:47PM |
0 |
Less aggressive on the first allocation of CSR if detecting an early exit |
| 12:33PM |
2 |
Update control flow graph when splitting a machine basic block? |
| 12:23PM |
0 |
[RFC] Making .eh_frame more linker-friendly |
| 11:41AM |
2 |
[RFC] Making .eh_frame more linker-friendly |
| 12:05AM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| |
| Thursday November 9 2017 |
| Time | Replies | Subject |
|---|
| 11:53PM |
0 |
CFG normalization: avoiding `br i1 false` |
| 11:38PM |
2 |
CFG normalization: avoiding `br i1 false` |
| 11:21PM |
2 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 10:53PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 9:37PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 9:31PM |
0 |
Experiment on how to improve our temporary file handing. |
| 9:13PM |
10 |
Experiment on how to improve our temporary file handing. |
| 8:56PM |
0 |
svn checkout error on Windows |
| 8:44PM |
0 |
New LLVM License |
| 7:49PM |
0 |
Phabricator "buildable" indication |
| 7:41PM |
2 |
Phabricator "buildable" indication |
| 7:00PM |
0 |
Problem with 'sed' on one Windows bot? |
| 6:27PM |
2 |
Problem with 'sed' on one Windows bot? |
| 6:08PM |
0 |
Problem with 'sed' on one Windows bot? |
| 5:36PM |
0 |
svn checkout error on Windows |
| 4:00PM |
0 |
Is it ok to allocate > half of address space? |
| 2:16PM |
0 |
Phabricator "buildable" indication |
| 1:15PM |
1 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 12:41PM |
2 |
Get basic-block cycle cost from LLVM |
| 11:29AM |
0 |
[RFC] Making .eh_frame more linker-friendly |
| 7:31AM |
2 |
[GlobalISel] [X86] unable to legalize instruction |
| 1:46AM |
2 |
New LLVM License |
| 1:36AM |
0 |
[GlobalISel] [X86] unable to legalize instruction |
| |
| Wednesday November 8 2017 |
| Time | Replies | Subject |
|---|
| 11:59PM |
0 |
OrcJIT + CUDA Prototype for Cling |
| 11:18PM |
2 |
Is it ok to allocate > half of address space? |
| 11:00PM |
0 |
[RFC] Enable Partial Inliner by default |
| 10:31PM |
1 |
getting nowhere with thinLTO |
| 10:16PM |
2 |
Phabricator "buildable" indication |
| 10:06PM |
0 |
Is it ok to allocate > half of address space? |
| 9:10PM |
0 |
[RFC] ASan: patches to support 32-byte shadow granularity |
| 8:46PM |
0 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 8:05PM |
0 |
[GreenDragon] Restart of Green Dragon at 12:05PST Today |
| 6:55PM |
2 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 6:30PM |
0 |
Is it ok to allocate > half of address space? |
| 6:13PM |
2 |
Is it ok to allocate > half of address space? |
| 5:41PM |
0 |
Is it ok to allocate > half of address space? |
| 5:33PM |
0 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 5:29PM |
0 |
[RFC] Setting the current debug loc when the insertion point changes |
| 5:24PM |
5 |
Is it ok to allocate > half of address space? |
| 2:10PM |
1 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 12:53PM |
0 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 12:00PM |
0 |
Debug info for Cuda |
| 11:43AM |
2 |
Debug info for Cuda |
| 10:34AM |
0 |
Debug info for Cuda |
| 9:05AM |
0 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 8:56AM |
0 |
[PATCH for-next 7/9] coverage: introduce support for llvm profiling |
| 8:38AM |
1 |
[PATCH for-next 7/9] coverage: introduce support for llvm profiling |
| 4:49AM |
2 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 4:16AM |
0 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 3:39AM |
2 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 2:59AM |
0 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 2:27AM |
6 |
[RFC] lld: Dropping TLS relaxations in favor of TLSDESC |
| 2:00AM |
0 |
A lot of -Wcast-qual warning when bootstrapping clang+compiler-rt on Mac. |
| 12:50AM |
3 |
[RFC] ASan: patches to support 32-byte shadow granularity |
| 12:42AM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| |
| Tuesday November 7 2017 |
| Time | Replies | Subject |
|---|
| 11:22PM |
2 |
Problem with 'sed' on one Windows bot? |
| 11:10PM |
0 |
Problem with 'sed' on one Windows bot? |
| 10:41PM |
4 |
Problem with 'sed' on one Windows bot? |
| 8:19PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 8:08PM |
0 |
Questions about code-size optimizations in ARM backend |
| 5:06PM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 5:02PM |
4 |
Questions about code-size optimizations in ARM backend |
| 4:19PM |
0 |
[RFC] Enable Partial Inliner by default |
| 4:04PM |
0 |
RFC: Debug info for Cuda |
| 3:45PM |
1 |
FW: clarification needed for the constrained fp implementation. |
| 3:27PM |
1 |
Mapping between instruction ins/outs to instruction bits-field |
| 1:51PM |
0 |
Set InstrItinData for RegPair |
| 9:22AM |
0 |
LLVM Compiler Social Zurich - November 9, 2017 - RISC-V @ETH Tech talk |
| 9:02AM |
2 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 2:49AM |
0 |
Does the ORC JIT on Linux eliminate frame pointers - if so - how does one disable this? |
| |
| Monday November 6 2017 |
| Time | Replies | Subject |
|---|
| 11:32PM |
2 |
[RFC] Setting the current debug loc when the insertion point changes |
| 10:58PM |
0 |
[RFC] Setting the current debug loc when the insertion point changes |
| 10:50PM |
2 |
[RFC] Setting the current debug loc when the insertion point changes |
| 10:32PM |
0 |
[RFC] Setting the current debug loc when the insertion point changes |
| 10:19PM |
3 |
[RFC] Setting the current debug loc when the insertion point changes |
| 9:49PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 9:37PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 9:35PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 8:43PM |
0 |
LLVM Weekly - #201, Nov 6th 2017 |
| 8:28PM |
3 |
ORC JIT and multithreading |
| 8:03PM |
2 |
Debug info for Cuda |
| 7:56PM |
0 |
Debug info for Cuda |
| 7:43PM |
0 |
FW: clarification needed for the constrained fp implementation. |
| 6:51PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 6:38PM |
3 |
PSA: debuginfo-tests workflow changing slightly |
| 6:37PM |
5 |
RFC: Debug info for Cuda |
| 6:31PM |
0 |
PowerPC64 Diassembler |
| 6:03PM |
0 |
lld: sigbus error handling |
| 4:58PM |
0 |
calling va_arg functions on win32 seems to require explicit stack alignment? |
| 4:51PM |
0 |
Can we start using std::to_string? |
| 3:07PM |
0 |
returns_twice / noreturn |
| 2:51PM |
0 |
Target Specific LTO Machine Pass |
| 2:03PM |
2 |
Target Specific LTO Machine Pass |
| 1:50PM |
2 |
Conditional includes in TableGen? |
| 11:35AM |
1 |
Two-stage build w/ ninja - Tests still use stage1 compiler / linker ? |
| 11:26AM |
0 |
Two-stage build w/ ninja - Tests still use stage1 compiler / linker ? |
| 2:22AM |
2 |
returns_twice / noreturn |
| 1:23AM |
1 |
What pattern string corresponds to CopyToReg? |
| |
| Sunday November 5 2017 |
| Time | Replies | Subject |
|---|
| 9:01PM |
0 |
returns_twice / noreturn |
| 4:58PM |
2 |
calling va_arg functions on win32 seems to require explicit stack alignment? |
| 10:53AM |
2 |
Two-stage build w/ ninja - Tests still use stage1 compiler / linker ? |
| 8:22AM |
0 |
What pattern string corresponds to CopyToReg? |
| 4:56AM |
2 |
What pattern string corresponds to CopyToReg? |
| 4:23AM |
0 |
What pattern string corresponds to CopyToReg? |
| 3:00AM |
2 |
What pattern string corresponds to CopyToReg? |
| 2:22AM |
0 |
What pattern string corresponds to CopyToReg? |
| 2:02AM |
2 |
What pattern string corresponds to CopyToReg? |
| |
| Saturday November 4 2017 |
| Time | Replies | Subject |
|---|
| 11:28PM |
0 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 10:49PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 10:28PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 10:12PM |
2 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 8:58PM |
0 |
RFC: We need to explicitly state that some functions are reserved by LLVM |
| 7:01PM |
1 |
[Sanitizer] Sanitizer does not identify violation |
| 4:34AM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 4:18AM |
3 |
PSA: debuginfo-tests workflow changing slightly |
| 1:12AM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 1:09AM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 1:06AM |
3 |
returns_twice / noreturn |
| 1:00AM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 12:57AM |
0 |
returns_twice / noreturn |
| 12:54AM |
2 |
returns_twice / noreturn |
| 12:45AM |
2 |
FW: clarification needed for the constrained fp implementation. |
| 12:39AM |
0 |
returns_twice / noreturn |
| 12:20AM |
2 |
returns_twice / noreturn |
| |
| Friday November 3 2017 |
| Time | Replies | Subject |
|---|
| 10:30PM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 10:26PM |
0 |
FW: clarification needed for the constrained fp implementation. |
| 10:21PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 9:57PM |
1 |
byval vs. explicitly coded copy |
| 8:29PM |
2 |
FW: clarification needed for the constrained fp implementation. |
| 8:00PM |
0 |
[RFC] Enable Partial Inliner by default |
| 4:40PM |
0 |
[RFC] Enable Partial Inliner by default |
| 4:36PM |
0 |
[RFC] Enable Partial Inliner by default |
| 4:21PM |
0 |
[RFC] Enable Partial Inliner by default |
| 2:09PM |
0 |
microbenchmark shows 3-6x perf loss w/ LLVM vs GCC at -O3, >1.5x w/ -flto |
| 1:34PM |
0 |
Publication Request: The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend |
| 7:14AM |
0 |
ARMConstantIslands: Can a basic block that ends with a conditional branch fall through to the next basic block? |
| 6:57AM |
1 |
slides from the LLVM October Meeting? |
| 5:15AM |
0 |
RFC: Splitting <Target>DAGISel.inc into declarations and definitions |
| 4:47AM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 4:24AM |
1 |
ScaffCC (A Framework for Compilation and Analysis of Quantum Computing Programs) migrated to LLVM 6.0 |
| 2:40AM |
0 |
Possible bugs in class ARMConstantIslands |
| 2:18AM |
2 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 2:17AM |
0 |
llvm-dev Digest, Vol 161, Issue 7 |
| 2:04AM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| |
| Thursday November 2 2017 |
| Time | Replies | Subject |
|---|
| 11:31PM |
0 |
[RFC] Enable Partial Inliner by default |
| 10:50PM |
0 |
[RFC] Enable Partial Inliner by default |
| 10:44PM |
1 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 10:05PM |
13 |
[RFC] Enable Partial Inliner by default |
| 9:26PM |
1 |
[RFC] Enable Partial Inliner by default |
| 8:12PM |
2 |
RFC: Splitting <Target>DAGISel.inc into declarations and definitions |
| 7:53PM |
0 |
[cfe-dev] 5.0.1-rc1 has been tagged |
| 6:17PM |
2 |
RFC: Generate plain !tbaa tags in place of !tbaa.struct ones |
| 3:22PM |
8 |
5.0.1-rc1 has been tagged |
| 1:49PM |
1 |
Possible bugs in class ARMConstantIslands |
| 11:57AM |
0 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 10:09AM |
0 |
Why am I getting FrameIndex:i64<0> when I have no i64's? |
| 4:20AM |
2 |
Why am I getting FrameIndex:i64<0> when I have no i64's? |
| 4:01AM |
2 |
Publication Request: The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend |
| 3:58AM |
0 |
Synopsys Hiring LLVM ARC Code Generation & Optimization Expert for backend compiler |
| 3:54AM |
0 |
RFC: Generate plain !tbaa tags in place of !tbaa.struct ones |
| 3:41AM |
0 |
An ambiguity in TBAA info format |
| 2:23AM |
0 |
Preserving Knowledge about Jump Tables |
| |
| Wednesday November 1 2017 |
| Time | Replies | Subject |
|---|
| 11:35PM |
5 |
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available |
| 10:47PM |
0 |
[lld] Flavour option purpose |
| 10:04PM |
0 |
Publication - Devirtualization in LLVM |
| 9:26PM |
0 |
llvm.gcroot trouble with non-i8* allocas |
| 8:26PM |
0 |
[VIDEO] Yegor Derevenets - On Decompilation (LLVM Social Berlin #9, 27.07.2017) |
| 8:11PM |
1 |
elf2yaml document structure, for dynamic symbols |
| 8:04PM |
0 |
Reaching definitions on Machine IR post register allocation |
| 7:49PM |
1 |
Cross compiling for Baremetal ARM without using GCC |
| 7:40PM |
0 |
elf2yaml document structure, for dynamic symbols |
| 7:36PM |
2 |
[lld] Flavour option purpose |
| 7:33PM |
1 |
Help building compiler-rt for a new cross target? |
| 7:16PM |
0 |
[lld] Flavour option purpose |
| 7:08PM |
2 |
[lld] Flavour option purpose |
| 6:56PM |
2 |
elf2yaml document structure, for dynamic symbols |
| 6:29PM |
0 |
elf2yaml document structure, for dynamic symbols |
| 5:43PM |
2 |
elf2yaml document structure, for dynamic symbols |
| 4:29PM |
0 |
[lld] Flavour option purpose |
| 4:24PM |
0 |
Using C++14 code in LLVM |
| 3:36PM |
0 |
[RFC] ASan: patches to support 32-byte shadow granularity |
| 1:19PM |
0 |
Status of llvm.invariant.{start|end} |
| 12:13PM |
0 |
Using C++14 code in LLVM |
| 12:02PM |
0 |
Cross compiling for Baremetal ARM without using GCC |
| 11:48AM |
0 |
Cross compiling for Baremetal ARM without using GCC |
| 9:59AM |
2 |
llvm.gcroot trouble with non-i8* allocas |
| 7:47AM |
0 |
Using C++14 code in LLVM |
| 7:30AM |
0 |
shadow-stack and llvm_gc_root_chain linkage when using JIT |
| 6:23AM |
4 |
Using C++14 code in LLVM |
| 5:30AM |
0 |
Using C++14 code in LLVM |
| 5:16AM |
0 |
A query language for LLVM IR (XPath) |
| 4:24AM |
2 |
Reaching definitions on Machine IR post register allocation |
| 1:06AM |
1 |
Using C++14 code in LLVM |