| Sunday December 31 2017 |
| Time | Replies | Subject |
|---|
| 5:18AM |
0 |
Questions about writing refactoring actions with LLVM |
| 3:49AM |
0 |
Submitting patches for LLVM -- llvm-commits vs. Phabricator? |
| |
| Saturday December 30 2017 |
| Time | Replies | Subject |
|---|
| 8:56PM |
0 |
No tags in the Git mirrors |
| 8:39PM |
3 |
No tags in the Git mirrors |
| 8:27PM |
0 |
No tags in the Git mirrors |
| 8:11PM |
0 |
Issues with omp simd |
| 7:49PM |
1 |
Issues with omp simd |
| 7:26PM |
0 |
Issues with omp simd |
| 7:19PM |
3 |
Issues with omp simd |
| 7:01PM |
0 |
Issues with omp simd |
| 5:08PM |
2 |
Issues with omp simd |
| 3:33PM |
0 |
multiple definitions |
| 2:28PM |
2 |
No tags in the Git mirrors |
| 2:21PM |
3 |
Submitting patches for LLVM -- llvm-commits vs. Phabricator? |
| 12:29AM |
1 |
RFC: Default path for cross-compiled runtimes |
| |
| Friday December 29 2017 |
| Time | Replies | Subject |
|---|
| 4:34PM |
0 |
Canonical way to handle zero registers? |
| 7:26AM |
0 |
Retrieve grid variable name in CUDA kernel call |
| 2:02AM |
3 |
Canonical way to handle zero registers? |
| 12:32AM |
0 |
ASan's FakeStack with a garbage-collected language |
| 12:08AM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| |
| Thursday December 28 2017 |
| Time | Replies | Subject |
|---|
| 6:12PM |
1 |
Upstreaming utils/kate/llvm.xml |
| 6:04PM |
0 |
Upstreaming utils/kate/llvm.xml |
| 3:58PM |
0 |
Help compiling LLVM 5.0.0 with MSVS 14.0 |
| 12:07PM |
1 |
bidirectional map |
| |
| Wednesday December 27 2017 |
| Time | Replies | Subject |
|---|
| 10:00PM |
0 |
Canonical way to handle zero registers? |
| 1:05PM |
0 |
[6.0.0 Release] One week to the branch |
| 12:56AM |
1 |
Convert MachineInstr to MCInst in AsmPrinter.cpp |
| 12:40AM |
1 |
Wrapper functions for standard library functions |
| |
| Tuesday December 26 2017 |
| Time | Replies | Subject |
|---|
| 11:42PM |
2 |
Canonical way to handle zero registers? |
| 11:29PM |
0 |
Proposal: On re-purposing/reorganizing MIR sigils ('&', '$', '%'). |
| 10:37PM |
0 |
Clang driver for OpenMP target offloading |
| 10:23PM |
1 |
Bootstrapping LLVM+LLD with GCC toolchain failure |
| 6:57PM |
3 |
Upstreaming utils/kate/llvm.xml |
| 3:24PM |
2 |
Regression tests |
| 3:14PM |
0 |
Bootstrapping LLVM+LLD with GCC toolchain failure |
| 12:30PM |
0 |
Contributing to LLVM |
| 11:17AM |
1 |
How to implement lowerReturn for poring GlobalISel to RISCV? |
| 11:00AM |
2 |
Bootstrapping LLVM+LLD with GCC toolchain failure |
| 10:13AM |
3 |
Why is remalloc not marked as noalias? |
| 9:01AM |
0 |
Issues with omp simd |
| |
| Monday December 25 2017 |
| Time | Replies | Subject |
|---|
| 9:21PM |
3 |
Beginner Bugs - Need help tagging |
| 7:18PM |
2 |
Proposal: On re-purposing/reorganizing MIR sigils ('&', '$', '%'). |
| 6:10PM |
0 |
Beginner Bugs - Need help tagging |
| 2:16PM |
0 |
no member named 'real_shmctl' in namespace '__interception' |
| 10:22AM |
0 |
LLVM Weekly - #208, Dec 25th 2017 |
| |
| Sunday December 24 2017 |
| Time | Replies | Subject |
|---|
| 10:44PM |
0 |
Contributing to LLVM |
| 5:33PM |
0 |
Canonical way to handle zero registers? |
| 1:56PM |
3 |
Contributing to LLVM |
| 1:25PM |
0 |
BackendUtil's EmitAssemblyHelper::EmitAssembly generated call inwrong order |
| 8:16AM |
0 |
Canonical way to handle zero registers? |
| 4:45AM |
0 |
BackendUtil's EmitAssemblyHelper::EmitAssembly generated call in wrong order |
| 4:43AM |
4 |
Canonical way to handle zero registers? |
| 4:13AM |
1 |
BackendUtil's EmitAssemblyHelper::EmitAssembly generated call in wrong order |
| 3:47AM |
0 |
BackendUtil's EmitAssemblyHelper::EmitAssembly generated call in wrong order |
| |
| Saturday December 23 2017 |
| Time | Replies | Subject |
|---|
| 7:56PM |
0 |
Hoisting in the presence of volatile loads. |
| 5:50PM |
1 |
Hoisting in the presence of volatile loads. |
| 2:39PM |
0 |
Hoisting in the presence of volatile loads. |
| 1:42PM |
2 |
Hoisting in the presence of volatile loads. |
| |
| Friday December 22 2017 |
| Time | Replies | Subject |
|---|
| 11:59PM |
0 |
Pass ordering - GVN vs. loop optimizations |
| 11:53PM |
0 |
Hoisting in the presence of volatile loads. |
| 10:17PM |
0 |
Canonical way to handle zero registers? |
| 8:24PM |
0 |
Opcodes with 32-bit pair vs 64-bit register operands |
| 3:14PM |
1 |
lib Fuzzer |
| 2:56PM |
1 |
pie and sanitizers |
| 2:28PM |
0 |
DBG_VALUE insertion for spills breaks bundles |
| 5:22AM |
4 |
Canonical way to handle zero registers? |
| |
| Thursday December 21 2017 |
| Time | Replies | Subject |
|---|
| 8:24PM |
2 |
Pass ordering - GVN vs. loop optimizations |
| 6:53PM |
0 |
How to implement lowerReturn for poring GlobalISel to RISCV? |
| 5:14PM |
1 |
llc: Unknown command line argument '-debug-only=isel' |
| 3:56PM |
0 |
Dropping COMDAT with LTO |
| 3:54PM |
0 |
llc: Unknown command line argument '-debug-only=isel' |
| 3:47PM |
0 |
llc: Unknown command line argument '-debug-only=isel' |
| 3:46PM |
0 |
llc: Unknown command line argument '-debug-only=isel' |
| 3:39PM |
3 |
llc: Unknown command line argument '-debug-only=isel' |
| 3:14PM |
5 |
llc: Unknown command line argument '-debug-only=isel' |
| 1:08PM |
0 |
Dominator tree side effect or intentional |
| 11:09AM |
0 |
Register Allocation Graph Coloring algorithm and Others |
| 10:11AM |
1 |
How to implement lowerReturn for poring GlobalISel to RISCV? |
| 8:32AM |
2 |
How to implement lowerReturn for poring GlobalISel to RISCV? |
| 5:51AM |
1 |
Query on i128 type tests written for memset |
| 5:17AM |
4 |
Hoisting in the presence of volatile loads. |
| 5:03AM |
2 |
How to implement lowerReturn for poring GlobalISel to RISCV? |
| 3:30AM |
1 |
Question about pickTracePred() in MachineTraceMetrics |
| 1:23AM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| |
| Wednesday December 20 2017 |
| Time | Replies | Subject |
|---|
| 10:59PM |
2 |
Dropping COMDAT with LTO |
| 9:49PM |
0 |
Hoisting in the presence of volatile loads. |
| 8:38PM |
0 |
Question about : lprofValueProfNodes |
| 7:50PM |
4 |
Hoisting in the presence of volatile loads. |
| 7:37PM |
0 |
Hoisting in the presence of volatile loads. |
| 7:30PM |
1 |
RFC: Exposing TargetTransformInfo factories from TargetMachine |
| 7:24PM |
1 |
Question about register allocator error |
| 5:51PM |
0 |
[GlobalISel] gen-global-isel failed to work |
| 5:50PM |
2 |
Hoisting in the presence of volatile loads. |
| 5:25PM |
0 |
Register Allocation Graph Coloring algorithm and Others |
| 2:46PM |
2 |
[GlobalISel] gen-global-isel failed to work |
| 1:33PM |
0 |
Hoisting in the presence of volatile loads. |
| 1:00PM |
1 |
Generating SPIR |
| 11:41AM |
0 |
[GlobalISel] gen-global-isel failed to work |
| 10:44AM |
1 |
[GlobalISel] gen-global-isel failed to work |
| 10:35AM |
0 |
[GlobalISel] gen-global-isel failed to work |
| 10:25AM |
6 |
[GlobalISel] gen-global-isel failed to work |
| 9:51AM |
1 |
possible violation of the LLVM-license in commercial product |
| 6:47AM |
1 |
[cfe-dev] LLVM 5.0.1 -final has been tagged |
| 2:30AM |
0 |
how to use sampling profiler outputs with opt |
| 2:28AM |
0 |
[cfe-dev] LLVM 5.0.1 -final has been tagged |
| 1:37AM |
2 |
Question about : lprofValueProfNodes |
| 1:29AM |
0 |
Question about : lprofValueProfNodes |
| 1:16AM |
2 |
Question about : lprofValueProfNodes |
| 1:14AM |
3 |
Hoisting in the presence of volatile loads. |
| |
| Tuesday December 19 2017 |
| Time | Replies | Subject |
|---|
| 8:33PM |
0 |
RFC: Default path for cross-compiled runtimes |
| 7:53PM |
2 |
RFC: Default path for cross-compiled runtimes |
| 7:31PM |
0 |
Question about : lprofValueProfNodes |
| 6:26PM |
3 |
Question about : lprofValueProfNodes |
| 5:31PM |
0 |
MemorySSA question |
| 5:26PM |
2 |
MemorySSA question |
| 5:25PM |
1 |
MemorySSA question |
| 5:17PM |
0 |
MemorySSA question |
| 5:10PM |
0 |
MemorySSA question |
| 4:33PM |
0 |
RFC: Default path for cross-compiled runtimes |
| 4:15PM |
3 |
RFC: Default path for cross-compiled runtimes |
| 4:13PM |
3 |
DBG_VALUE insertion for spills breaks bundles |
| 2:27PM |
1 |
Generating SPIR |
| 2:03PM |
0 |
Generating SPIR |
| 1:28PM |
2 |
[GlobalISel] gen-global-isel failed to work |
| 11:51AM |
1 |
Portable Computing Language (pocl) v1.0 released |
| 11:13AM |
4 |
MemorySSA question |
| 10:53AM |
1 |
[GlobalISel] gen-global-isel failed to work |
| 9:36AM |
0 |
[GlobalISel] gen-global-isel failed to work |
| 8:59AM |
0 |
Update documentation about Module::addTypeName |
| 4:16AM |
0 |
Register Allocation Graph Coloring algorithm and Others |
| 3:24AM |
1 |
A code layout related side-effect introduced by rL318299 |
| 3:10AM |
0 |
A code layout related side-effect introduced by rL318299 |
| 3:03AM |
4 |
Register Allocation Graph Coloring algorithm and Others |
| 2:26AM |
0 |
RFC: Exposing TargetTransformInfo factories from TargetMachine |
| 2:07AM |
0 |
Register Allocation Graph Coloring algorithm and Others |
| 2:03AM |
2 |
A code layout related side-effect introduced by rL318299 |
| 1:46AM |
0 |
A code layout related side-effect introduced by rL318299 |
| 1:01AM |
2 |
A code layout related side-effect introduced by rL318299 |
| 12:52AM |
1 |
Question about generated code for x86 vpgather* intrinsics |
| 12:26AM |
1 |
AddRec.getStepRecurrence |
| 12:21AM |
0 |
A code layout related side-effect introduced by rL318299 |
| 12:14AM |
4 |
A code layout related side-effect introduced by rL318299 |
| 12:07AM |
3 |
Register Allocation Graph Coloring algorithm and Others |
| |
| Monday December 18 2017 |
| Time | Replies | Subject |
|---|
| 7:14PM |
2 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 7:12PM |
0 |
LLVM Weekly - #207, Dec 18th 2017 |
| 5:52PM |
1 |
Register Allocation Graph Coloring algorithm and Others |
| 5:44PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 4:41PM |
0 |
Register Allocation Graph Coloring algorithm and Others |
| 3:25PM |
2 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 2:11PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 1:47PM |
1 |
Immediates in intrinsics |
| 12:37PM |
2 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 9:01AM |
0 |
LLVM 5.0.1 -final has been tagged |
| 5:01AM |
0 |
Immediates in intrinsics |
| 4:26AM |
3 |
Immediates in intrinsics |
| |
| Sunday December 17 2017 |
| Time | Replies | Subject |
|---|
| 6:28PM |
0 |
Removing constants from a constant array? |
| 5:19AM |
10 |
LLVM 5.0.1 -final has been tagged |
| 4:08AM |
2 |
Removing constants from a constant array? |
| 2:40AM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 12:58AM |
2 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| |
| Saturday December 16 2017 |
| Time | Replies | Subject |
|---|
| 9:53PM |
0 |
Clang 5, UBsan, runtime error: addition of unsigned offset to X overflowed to Y |
| 8:18PM |
3 |
Clang 5, UBsan, runtime error: addition of unsigned offset to X overflowed to Y |
| 7:40PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 7:27PM |
3 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 7:25PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 12:08PM |
2 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 4:10AM |
1 |
RFC: Synthetic function entry counts |
| 3:25AM |
0 |
Replace call stack with an equivalent on the heap? |
| 1:51AM |
2 |
Replace call stack with an equivalent on the heap? |
| 1:50AM |
0 |
RFC: Synthetic function entry counts |
| |
| Friday December 15 2017 |
| Time | Replies | Subject |
|---|
| 10:49PM |
0 |
llvm-config output on MacOS |
| 10:28PM |
2 |
llvm-config output on MacOS |
| 9:28PM |
2 |
RFC: Synthetic function entry counts |
| 8:45PM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 8:23PM |
2 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 7:56PM |
0 |
RFC: Synthetic function entry counts |
| 7:53PM |
0 |
x86-64 unwind additions |
| 7:31PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 7:27PM |
2 |
RFC: Synthetic function entry counts |
| 7:13PM |
0 |
RFC: Synthetic function entry counts |
| 6:58PM |
3 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 6:33PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 6:22PM |
2 |
RFC: Synthetic function entry counts |
| 6:12PM |
4 |
RFC: Exposing TargetTransformInfo factories from TargetMachine |
| 6:06PM |
0 |
[Openmp-dev] [6.0.0 Release] Scheduling the release |
| 5:46PM |
0 |
llvm-config output on MacOS |
| 3:47PM |
3 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 3:22PM |
0 |
[lld] Well lld support some advanced features like gnu linker in macOS? |
| 2:51PM |
1 |
MachineInstr - different treatment of subregs for checking mods and reads |
| 1:30PM |
0 |
RFC: Exposing TargetTransformInfo factories from TargetMachine |
| 11:40AM |
0 |
InstAlias with tied operands - can it be supported? |
| 9:55AM |
3 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 8:22AM |
0 |
RFC: Synthetic function entry counts |
| 7:34AM |
1 |
[RFC] Add TargetTransformInfo::isAllocaPtrValueNonZero and let ValueTracking depend on TargetTransformInfo |
| 7:22AM |
2 |
RFC: Exposing TargetTransformInfo factories from TargetMachine |
| 6:42AM |
2 |
[Openmp-dev] [6.0.0 Release] Scheduling the release |
| 6:24AM |
2 |
llvm-config output on MacOS |
| 6:20AM |
0 |
[RFC] Add TargetTransformInfo::isAllocaPtrValueNonZero and let ValueTracking depend on TargetTransformInfo |
| 5:14AM |
3 |
[RFC] Add TargetTransformInfo::isAllocaPtrValueNonZero and let ValueTracking depend on TargetTransformInfo |
| 4:58AM |
0 |
Register Allocation Graph Coloring algorithm and Others |
| 4:40AM |
0 |
Register Allocation Graph Coloring algorithm and Others |
| 4:03AM |
0 |
[lld] bug detecting undefined symbols in shared libraries |
| 3:18AM |
8 |
Register Allocation Graph Coloring algorithm and Others |
| 2:12AM |
2 |
InstAlias with tied operands - can it be supported? |
| 1:28AM |
0 |
[RFC] Add TargetTransformInfo::isAllocaPtrValueNonZero and let ValueTracking depend on TargetTransformInfo |
| 12:52AM |
0 |
LLVM 5.0.1-final coming on Friday |
| |
| Thursday December 14 2017 |
| Time | Replies | Subject |
|---|
| 10:47PM |
0 |
LLVM Pass that does not print Pass Summary |
| 9:56PM |
0 |
[6.0.0 Release] Scheduling the release |
| 9:49PM |
3 |
[RFC][LV][VPlan] Proposal for Outer Loop Vectorization Implementation Plan |
| 9:49PM |
3 |
[RFC] Add TargetTransformInfo::isAllocaPtrValueNonZero and let ValueTracking depend on TargetTransformInfo |
| 9:44PM |
1 |
RFC: Synthetic function entry counts |
| 9:34PM |
0 |
Help adding entries to .symtab |
| 9:09PM |
0 |
[RFC][LV][VPlan] Proposal for Outer Loop Vectorization Implementation Plan |
| 9:06PM |
0 |
[RFC] Add TargetTransformInfo::isAllocaPtrValueNonZero and let ValueTracking depend on TargetTransformInfo |
| 9:03PM |
0 |
RFC: Synthetic function entry counts |
| 8:59PM |
2 |
Help adding entries to .symtab |
| 8:32PM |
2 |
[RFC] Add TargetTransformInfo::isAllocaPtrValueNonZero and let ValueTracking depend on TargetTransformInfo |
| 7:49PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 7:03PM |
0 |
Help adding entries to .symtab |
| 4:39PM |
0 |
[intern ad] Internship on Code Obfuscation @ Quarkslab, France |
| 3:22PM |
2 |
x86-64 unwind additions |
| 11:14AM |
0 |
[LV][VPlan] Status Update on VPlan ----- where we are currently, and what's ahead of us |
| 10:36AM |
2 |
Help adding entries to .symtab |
| 8:11AM |
0 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 7:22AM |
2 |
[lld] Well lld support some advanced features like gnu linker in macOS? |
| 4:18AM |
1 |
Interaction of --disable-llvm-passes and -O0 |
| 2:31AM |
0 |
devirtualization with new-PM pipeline |
| 2:26AM |
2 |
devirtualization with new-PM pipeline |
| |
| Wednesday December 13 2017 |
| Time | Replies | Subject |
|---|
| 10:06PM |
1 |
instcombine and alias analysis (new-PM) |
| 9:52PM |
1 |
stale docs at https://clang.llvm.org/docs? |
| 6:58PM |
0 |
Job ad: Compiler Engineer at Google |
| 1:47AM |
1 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 1:42AM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 1:11AM |
2 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 1:02AM |
5 |
RFC: Synthetic function entry counts |
| 12:53AM |
2 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| |
| Tuesday December 12 2017 |
| Time | Replies | Subject |
|---|
| 9:38PM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 8:57PM |
3 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 8:22PM |
0 |
TypeExpandInteger for vectors? |
| 8:08PM |
1 |
Who wants faster LLVM/Clang builds? |
| 7:50PM |
0 |
File/module scope inline assembly |
| 6:33PM |
0 |
Extending llvm::iterator_range |
| 3:26PM |
2 |
TypeExpandInteger for vectors? |
| 1:30PM |
3 |
File/module scope inline assembly |
| 5:04AM |
1 |
[Release-testers] 5.0.1-rc3 has been tagged |
| 3:14AM |
0 |
Who wants faster LLVM/Clang builds? |
| 2:54AM |
0 |
TypeExpandInteger for vectors? |
| 2:14AM |
0 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 1:08AM |
0 |
[Release-testers] 5.0.1-rc3 has been tagged |
| 12:29AM |
2 |
Extending llvm::iterator_range |
| 12:17AM |
0 |
New x86 instruction with opcode 0x0F 0x7A |
| 12:05AM |
0 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 12:04AM |
3 |
[lld] bug detecting undefined symbols in shared libraries |
| |
| Monday December 11 2017 |
| Time | Replies | Subject |
|---|
| 11:54PM |
0 |
[lld] bug detecting undefined symbols in shared libraries |
| 11:50PM |
2 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 11:39PM |
2 |
[lld] bug detecting undefined symbols in shared libraries |
| 9:39PM |
0 |
LLVM Weekly - #206, Dec 11th 2017 |
| 8:37PM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 6:41PM |
0 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 5:14PM |
2 |
New x86 instruction with opcode 0x0F 0x7A |
| 5:08PM |
0 |
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! |
| 1:12PM |
1 |
llvm-dev Digest, Vol 162, Issue 35 |
| 7:57AM |
0 |
target porting : objdump is not giving proper registers. |
| 6:41AM |
2 |
target porting : objdump is not giving proper registers. |
| |
| Sunday December 10 2017 |
| Time | Replies | Subject |
|---|
| 10:55PM |
0 |
[Release-testers] 5.0.1-rc3 has been tagged |
| 3:40PM |
0 |
Global non-use of ISD::BR_CC and ISD::CONDCODE |
| 3:39PM |
3 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 6:12AM |
2 |
[Release-testers] 5.0.1-rc3 has been tagged |
| |
| Saturday December 9 2017 |
| Time | Replies | Subject |
|---|
| 11:32PM |
1 |
Request for commit |
| 11:06PM |
2 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 8:54PM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 12:51PM |
0 |
[Release-testers] 5.0.1-rc3 has been tagged |
| 12:47PM |
0 |
[RFC] Enable Partial Inliner by default |
| 6:36AM |
2 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 1:05AM |
0 |
5.0.1-rc3 has been tagged |
| 1:01AM |
2 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| |
| Friday December 8 2017 |
| Time | Replies | Subject |
|---|
| 10:05PM |
0 |
Help in generating Debug symbols |
| 9:53PM |
1 |
How to use LLVM-C to JIT-compile the floating-point identity function |
| 9:29PM |
4 |
Non-relocating GC with liveness tracking |
| 7:50PM |
0 |
Unresolved symbols in compiler-rt |
| 7:27PM |
3 |
Unresolved symbols in compiler-rt |
| 7:03PM |
0 |
May IR types be merged by llvm-link? |
| 6:05PM |
2 |
Help in generating Debug symbols |
| 6:04PM |
0 |
Issue with BUILD_SHARED_LIBS=ON |
| 5:20PM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 3:53PM |
3 |
Parse LLVM IR using LLVM C API |
| 1:18PM |
0 |
Help in generating Debug symbols |
| 9:37AM |
3 |
Issue with BUILD_SHARED_LIBS=ON |
| 9:09AM |
2 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 6:51AM |
0 |
[AMDGPU] Strange results with different address spaces |
| 6:24AM |
2 |
Help in generating Debug symbols |
| |
| Thursday December 7 2017 |
| Time | Replies | Subject |
|---|
| 11:47PM |
7 |
5.0.1-rc3 has been tagged |
| 11:37PM |
0 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 10:51PM |
0 |
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section |
| 9:23PM |
0 |
How to count instructions in a function? |
| 9:16PM |
1 |
buildbot failure in LLVM on llvm-clang-x86_64-expensive-checks-win |
| 8:53PM |
0 |
buildbot failure in LLVM on llvm-clang-x86_64-expensive-checks-win |
| 8:20PM |
0 |
devirtualization with new-PM pipeline |
| 8:20PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 8:18PM |
0 |
Updating LLVM/Clang support for VS for VS2017 |
| 8:12PM |
2 |
Updating LLVM/Clang support for VS for VS2017 |
| 8:09PM |
2 |
devirtualization with new-PM pipeline |
| 7:52PM |
1 |
[lldb-dev] [6.0.0 Release] Scheduling the release |
| 7:50PM |
0 |
[6.0.0 Release] Scheduling the release |
| 5:12PM |
0 |
TargetSelect.h and layering |
| 5:09PM |
2 |
TargetSelect.h and layering |
| 3:08PM |
0 |
Updating LLVM/Clang support for VS for VS2017 |
| 2:31PM |
0 |
RISC-V LLVM sync-up conference calls |
| 12:57PM |
0 |
Publication and project for inclusion? |
| 12:47PM |
4 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 11:09AM |
1 |
[cfe-dev] XRay Trace of Clang, Loadable through Chrome Trace Viewer |
| 10:16AM |
3 |
May IR types be merged by llvm-link? |
| 2:36AM |
0 |
RFC: Generate plain !tbaa tags in place of !tbaa.struct ones |
| 2:16AM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 1:46AM |
1 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 1:14AM |
0 |
TargetSelect.h and layering |
| 1:09AM |
2 |
TargetSelect.h and layering |
| |
| Wednesday December 6 2017 |
| Time | Replies | Subject |
|---|
| 10:22PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 9:17PM |
3 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 9:06PM |
0 |
[lldb-dev] [6.0.0 Release] Scheduling the release |
| 8:28PM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 7:38PM |
2 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 7:05PM |
0 |
Question about visibility analysis for whole program devirtualization pass |
| 6:52PM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 6:45PM |
2 |
[AMDGPU] Strange results with different address spaces |
| 6:25PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 6:23PM |
3 |
PSA: debuginfo-tests workflow changing slightly |
| 6:21PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 6:13PM |
2 |
PSA: debuginfo-tests workflow changing slightly |
| 6:10PM |
0 |
PSA: debuginfo-tests workflow changing slightly |
| 5:40PM |
3 |
buildbot failure in LLVM on llvm-clang-x86_64-expensive-checks-win |
| 5:28PM |
8 |
[6.0.0 Release] Scheduling the release |
| 5:00PM |
0 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 4:48PM |
2 |
Question about visibility analysis for whole program devirtualization pass |
| 4:47PM |
0 |
[cfe-dev] XRay Trace of Clang, Loadable through Chrome Trace Viewer |
| 3:05PM |
3 |
Who wants faster LLVM/Clang builds? |
| 2:21PM |
1 |
[LV][VPlan] Status Update on VPlan ----- where we are currently, and what's ahead of us |
| 1:25PM |
1 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 12:59PM |
0 |
Adding a prologue to BB |
| 12:15PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 11:15AM |
4 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 9:44AM |
0 |
CCAssignToReg with range of registers |
| 9:37AM |
0 |
[LV][VPlan] Status Update on VPlan ----- where we are currently, and what's ahead of us |
| 8:45AM |
0 |
Who wants faster LLVM/Clang builds? |
| 8:32AM |
2 |
[RFC] Half-Precision Support in the Arm Backends |
| 7:28AM |
0 |
[AMDGPU] Strange results with different address spaces |
| 7:15AM |
2 |
[cfe-dev] Who wants faster LLVM/Clang builds? |
| 6:08AM |
0 |
Who wants faster LLVM/Clang builds? |
| 6:01AM |
1 |
Who wants faster LLVM/Clang builds? |
| 5:59AM |
2 |
Who wants faster LLVM/Clang builds? |
| 5:38AM |
0 |
Who wants faster LLVM/Clang builds? |
| 4:04AM |
1 |
Query regarding LLVM IR is SSA |
| 3:36AM |
0 |
Question about visibility analysis for whole program devirtualization pass |
| 3:14AM |
1 |
[LLD] Slow callstacks in gdb |
| 2:47AM |
0 |
[LLD] Slow callstacks in gdb |
| 2:22AM |
2 |
[LLD] Slow callstacks in gdb |
| 1:09AM |
3 |
[RFC][LV][VPlan] Proposal for Outer Loop Vectorization Implementation Plan |
| 12:21AM |
5 |
[LV][VPlan] Status Update on VPlan ----- where we are currently, and what's ahead of us |
| |
| Tuesday December 5 2017 |
| Time | Replies | Subject |
|---|
| 11:54PM |
0 |
December LLVM bay-area social is this Thursday! |
| 11:40PM |
9 |
Who wants faster LLVM/Clang builds? |
| 9:28PM |
0 |
[LLD] Slow callstacks in gdb |
| 9:22PM |
2 |
[LLD] Slow callstacks in gdb |
| 8:53PM |
0 |
5.0.1-rc2 has been tagged |
| 8:52PM |
2 |
[cfe-dev] XRay Trace of Clang, Loadable through Chrome Trace Viewer |
| 8:13PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 7:01PM |
2 |
[AMDGPU] Strange results with different address spaces |
| 6:53PM |
0 |
[AMDGPU] Strange results with different address spaces |
| 6:15PM |
0 |
[Intern Ad] Microsoft Research Cambridge |
| 6:12PM |
0 |
5.0.1-rc3 release on Thursday |
| 5:17PM |
0 |
[cfe-dev] XRay Trace of Clang, Loadable through Chrome Trace Viewer |
| 3:49PM |
2 |
XRay Trace of Clang, Loadable through Chrome Trace Viewer |
| 3:25PM |
1 |
MaxTargetFixupKind -- why is it so limiting? |
| 2:41PM |
0 |
Question about visibility analysis for whole program devirtualization pass |
| 12:09PM |
0 |
llvm-trunk: available files/directories are not found |
| 9:01AM |
0 |
[LLD] Slow callstacks in gdb |
| 7:51AM |
3 |
[AMDGPU] Strange results with different address spaces |
| 5:08AM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 4:58AM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD) |
| 1:37AM |
0 |
TargetSelect.h and layering |
| 12:54AM |
2 |
[LLD] Slow callstacks in gdb |
| 12:06AM |
0 |
CFG normalization: avoiding `br i1 false` |
| |
| Monday December 4 2017 |
| Time | Replies | Subject |
|---|
| 11:58PM |
2 |
[RFC] - Deduplication of debug information in linkers (LLD) |
| 11:44PM |
0 |
CFG normalization: avoiding `br i1 false` |
| 10:18PM |
0 |
Passes to add/validate synthetic debug info |
| 9:44PM |
2 |
Passes to add/validate synthetic debug info |
| 9:29PM |
1 |
Adding a string-argument Intrinsic |
| 9:23PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 9:20PM |
0 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 9:14PM |
0 |
LLVM Weekly - #205, Dec 4th 2017 |
| 8:20PM |
0 |
[RFC] Half-Precision Support in the Arm Backends |
| 6:49PM |
5 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 6:46PM |
2 |
RFC: Adding 'no-overflow' keyword to 'sdiv'\'udiv'instructions |
| 6:00PM |
1 |
[Release-testers] 5.0.1-rc2 has been tagged |
| 5:15PM |
1 |
5.0.1-rc2 has been tagged |
| 3:29PM |
0 |
JIT and atexit crash |
| 3:11PM |
5 |
[RFC] - Deduplication of debug information in linkers (LLD). |
| 2:59PM |
0 |
[Release-testers] 5.0.1-rc2 has been tagged |
| 2:53PM |
0 |
5.0.1-rc2 has been tagged |
| 2:44PM |
2 |
[RFC] Half-Precision Support in the Arm Backends |
| 8:38AM |
1 |
CodeExtractor buggy? |
| 8:14AM |
0 |
[LLD] Slow callstacks in gdb |
| |
| Sunday December 3 2017 |
| Time | Replies | Subject |
|---|
| 5:07PM |
0 |
CodeExtractor buggy? |
| 2:57PM |
0 |
RFC: Adding 'no-overflow' keyword to 'sdiv'\'udiv'instructions |
| 7:26AM |
0 |
Some strange i64 behavior with arm 32bit. (Raspberry Pi) |
| 6:44AM |
2 |
5.0.1-rc2 has been tagged |
| 5:35AM |
1 |
DIEnumerator *createEnumerator(StringRef Name, int64_t Val); // add APInt Val overload |
| 4:05AM |
0 |
question: access IR class Instruction from DAG SDValue |
| |
| Saturday December 2 2017 |
| Time | Replies | Subject |
|---|
| 8:59PM |
1 |
asan over WSL |
| 4:33PM |
2 |
[LLD] Slow callstacks in gdb |
| 1:20PM |
1 |
Schedules, latency and register liveness for complex instructions |
| 12:47PM |
0 |
Schedules, latency and register liveness for complex instructions |
| 11:47AM |
0 |
question: access IR class Instruction from DAG SDValue |
| 8:44AM |
0 |
Why negative to Clang Static Analyzer? |
| 7:26AM |
0 |
[LLD] Slow callstacks in gdb |
| 6:27AM |
0 |
Why negative to Clang Static Analyzer? |
| 12:23AM |
3 |
Generating SPIR |
| |
| Friday December 1 2017 |
| Time | Replies | Subject |
|---|
| 10:50PM |
1 |
gnu X sysv hash performance |
| 10:39PM |
0 |
CMake executable dependency woes |
| 10:07PM |
3 |
gnu X sysv hash performance |
| 9:55PM |
0 |
gnu X sysv hash performance |
| 9:41PM |
2 |
CMake executable dependency woes |
| 9:39PM |
0 |
LLVM buildmaster will be OFF today at 3 PM Pacific for maintenance |
| 9:26PM |
3 |
gnu X sysv hash performance |
| 9:20PM |
0 |
(no subject) |
| 9:17PM |
0 |
CMake executable dependency woes |
| 9:10PM |
0 |
Expose aliasing information in getModRefInfo (or viceversa?) |
| 6:47PM |
2 |
[Release-testers] 5.0.1-rc2 has been tagged |
| 6:18PM |
0 |
5.0.1-rc2 has been tagged |
| 6:00PM |
0 |
[Release-testers] 5.0.1-rc2 has been tagged |
| 5:34PM |
2 |
Schedules, latency and register liveness for complex instructions |
| 3:30PM |
0 |
[Release-testers] 5.0.1-rc2 has been tagged |
| 2:15PM |
2 |
Schedules, latency and register liveness for complex instructions |
| 11:58AM |
0 |
TwoAddressInstructionPass bug? |
| 11:54AM |
1 |
How to create a call to a MachineFunction |
| 11:14AM |
0 |
PPC64 Disassembler |
| 10:47AM |
0 |
[Release-testers] 5.0.1-rc2 has been tagged |
| 10:30AM |
2 |
Some strange i64 behavior with arm 32bit. (Raspberry Pi) |
| 9:07AM |
0 |
Using Scalar Evolution to Identify Expressions Evolving in terms of Loop induction variables |
| 8:26AM |
0 |
Some strange i64 behavior with arm 32bit. (Raspberry Pi) |
| 7:54AM |
2 |
Some strange i64 behavior with arm 32bit. (Raspberry Pi) |
| 5:44AM |
0 |
Using Scalar Evolution to Identify Expressions Evolving in terms of Loop induction variables |
| 4:50AM |
2 |
Using Scalar Evolution to Identify Expressions Evolving in terms of Loop induction variables |
| 2:05AM |
0 |
[Release-testers] 5.0.1-rc2 has been tagged |