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tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/mst/vhost.git linux-next head: 39c226b6b576b23d6d558331e6895f02b0892555 commit: 990055c63121520ad29deca72b1167b392563ddd [16/17] virtio-balloon: Add support for providing unused page reports to host config: riscv-allmodconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 7.4.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 990055c63121520ad29deca72b1167b392563ddd # s...

...piling risc-v programs. llvm-project version:dd8a2013dc1804be1b7d9cffacad2e984300bd22 Instructons to build LLVM+clang: ``` cmake -G Ninja -DCMAKE_INSTALL_PREFIX=/home/llvm/workspace/llvm/llvm-project/llvm_install -DCMAKE_BUILD_TYPE="Release" -DDEFAULT_SYSROOT="/home/llvm/workspace/riscv/riscv-tc-20200220/bin/riscv32-unknown-elf" -DGCC_INSTALL_PREFIX="/home/llvm/workspace/riscv/riscv-tc-20200220" -DLLVM_DEFAULT_TARGET_TRIPLE="riscv32-unknown-elf" -DLLVM_ENABLE_PROJECTS="clang;lld;libc" -DLLVM_TARGETS_TO_BUILD="RISCV" ../llvm ``` Instruc...

H all, I'm looking at generating PIC code for RISC-V in the context of Linux. Not sure if anyone is working on this already, any inputs are very welcome. I'm now looking at function calls which in the RISCV backend are represented via two pseudoinstructions RISCV::TAIL and RISCV::CALL. Currently those pseudos are lowered in MCCodeEmitter. They are expanded into AUIPC and JALR instructions and the first one needs a relocation, which for a static reloc model is R_RISCV_CALL but for PIC code should be R...

...experimental but I think it didn't go anywhere? Separately, do the listed patches sound okay for merging? Thanks, Hans On Fri, Jan 25, 2019 at 4:40 PM Bruce Hoult <brucehoult at sifive.com> wrote: > > In https://llvm.org/svn/llvm-project/llvm/branches/release_80 I find > that RISCV is still in LLVM_EXPERIMENTAL_TARGETS_TO_BUILD. not > LLVM_TARGETS_TO_BUILD. I thought people had agreed to change that in > this release? > > There are also at least a couple of fairly important patches that it > would be good to get back-ported into the release branch if possible &...

Hi, I would like to start a new porting of GlobalIsel for RISCV. An initial patch about GlobalIsel infrastructure for RISCV was ready now: https://reviews.llvm.org/D65219 There is another porting patch https://reviews.llvm.org/D41653 posted by Leslie Zhai at the end of 2017. I have checked with Leslie about the status of this patch.He has stopped developing i...

Hi all, I'm currently working on the implementation for LLVM of the RISCV Bit Manipulation ISA extension described by Clifford Wolf in the following presentation: https://content.riscv.org/wp-content/uploads/2019/06/17.10-b_wolf.pdf and the following document: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.90.pdf The aim is to provide the intrinsic fu...

*llvm-project version:dd8a2013dc1804be1b7d9cffacad2e984300bd22* *Instructons to build LLVM+clang:* ``` cmake -G Ninja -DCMAKE_INSTALL_PREFIX=/home/llvm/workspace/llvm/llvm-project/llvm_install -DCMAKE_BUILD_TYPE="Release" -DDEFAULT_SYSROOT="/home/llvm/workspace/riscv/riscv-tc-20200220/bin/riscv32-unknown-elf" -DGCC_INSTALL_PREFIX="/home/llvm/workspace/riscv/riscv-tc-20200220" -DLLVM_DEFAULT_TARGET_TRIPLE="riscv32-unknown-elf" -DLLVM_ENABLE_PROJECTS="clang;lld;libc" -DLLVM_TARGETS_TO_BUILD="RISCV" ../llvm ``` *When c...

...BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,                                   const Value *Val, unsigned VReg) const {   assert(!Val == !VReg && "Return value without a vreg");   MIRBuilder.buildInstr(BPF::RET);   return true; } But how to implement it for RISCV target? https://github.com/xiangzhai/llvm/commit/c49146edbbf655e97727e22e4a87a020fb8da6e5 Because there are separate trap return instructions[2] per privilege level: MRET, SRET, and URET. MRET is always provided, while SRET must be provided if supervisor mode is supported. URET is only provided...

...t update the accrued exception state. Clang does very well, with the exception of float to u64 and double to u64. They are currently the only two operations that fail the RISC-V QEMU tests, which is essentially testing all of the compiler floating point intrinsics. https://github.com/michaeljclark/riscv-meta/blob/ea306062bfd2f60a229daf6b04826cdeb2dfbe9d/meta/opcode-pseudocode-c#L132-L204 These are the tests that I am using to exercise clang and gcc FENV_ACCESS along with the C code in the link above. riscv-qemu-tests is a user-mode port of the RISC-V ISA conformance test suite. - https://github....

Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructions or at least to find a way to implement this relaxation...

...ions)[3].</p><p>[1] <a href="https://en.wikipedia.org/wiki/Carry-less_product">https://en.wikipedia.org/wiki/Carry-less_product</a><br /><a href="https://en.wikipedia.org/wiki/Carry-less_product%5B2%5D%20(page%2030)%20https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-0.92.pdf%5B3%5D%20https://www.bearssl.org/constanttime.html">[2] (page 30) </a><a href="https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-0.92.pdf">https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmani...

Hi, I am not sure if this is the right forum. Please direct me to the appropriate place if it isn't so. Please keep in CC as i am not subscribed to this mailing list. I am trying to test riscv llvm tools in QEMU using llvm testsuite. As a trial i am trying only the Single Source C Regression folder. The steps that i took are : ]$ cmake -DCMAKE_C_COMPILER=/opt/riscv-tools/bin/clang -DCMAKE_C_FLAGS="--target=riscv32 -march=rv32i -mabi=ilp32" -DCMAKE_CXX_COMPILER=/opt/riscv-tools...

...en defined for the CSRRW/CSRRS/CSRRC instructions. It would be convenient to have intrinsics for these to allow CSR manipulation directly from IR code. Interestingly, this seems to be true for PowerPC (no intrinsics for mfdcr/mtdcr) and X86 (no in/out) as well. Are there plans to define standard RISCV intrinsics for this? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190213/d8f473a9/attachment.html>

I tried to build LLVM to include the RISCV (experimental) target. I noticed that the instructions on the wiki were out of dat because they said to use '-DLLVM_TARGETS_TO_BUILD', but this gave a warning to use `LLVM_EXPERIMENTAL_TARGETS_TO_BUILD` as well (or instead?). So I compiled with these options: cmake -DCMAKE_BUILD_TYPE=Min...

...t; > there doesn't seem to be a strong motivation for requiring a custom LLVM build > > to force this. However, such unratified extensions shouldn't be accessible via > > normal RISC-V ISA naming strings (e.g. "rv32imafdc"), and instead flags of the > > form `-riscv-experimental-vector-ext` in LLVM and `-mexperimental-vector-ext` > > in Clang should be used (i.e. option 3)). We discussed this in our weekly call > > however, and there were voices advocating either option 2 or 3. Input welcome. > > > > If going down the option 3 route, th...

I am maintaining proprietary extensions to the RISCV backend for our custom application. I have defined intrinsics for many of the custom instructions. Against LLVM 7 this was working well. When I try to merge my changes into LLVM 10, I get: /home/dej/work/llvm_git/llvm-project/llvm/build/lib/Target/RISCV/RISCVGenGlobalISel.inc:11582:60: error: ‘...

...ileCheck/check-empty-tag.txt > LLVM :: FileCheck/dump-input-annotations.txt > LLVM :: FileCheck/no-multi-suffixes.txt > LLVM :: FileCheck/var-scope.txt > LLVM :: MC/AsmParser/expr-shr.s > LLVM :: MC/Mips/relocation-n64.s > LLVM :: MC/Mips/relocation.s > LLVM :: MC/RISCV/compressed-relocations.s > LLVM :: MC/RISCV/relocations.s > LLVM :: MC/RISCV/rv32b-aliases-valid.s > LLVM :: MC/RISCV/rv64b-aliases-valid.s > LLVM :: MC/RISCV/rva-aliases-valid.s > LLVM :: MC/RISCV/rvi-aliases-valid.s > LLVM :: Transforms/InstCombine/double-float-shrin...

...be properly handled. Note that RISC-V also handles alignment as part of relaxation, so it isn't really optional. For example: _start: mv a0, a0 .p2align 2 li a0, 0 The assembler inserts a 3-byte padding (note: this behavior isn't merged yet, see: https://github.com/riscv/riscv-binutils-gdb/pull/88): 00000000 <_start>: 0: 852a mv a0,a0 2: 00 01 00 # R_RISCV_ALIGN 2: R_RISCV_ALIGN *ABS*+0x3 5: 4501 li a0,0 The linker then remove 1 byte from pad...

...wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: > > %vl = call i32 @llvm.riscv.vsetvl(i32 %n) > > At the time of the talk (April 2019) LLVM support for the V extension was developed out-of-tree at https://github.com/hanna-kruppe/rvv-llvm . However, that repository is archived now and the README file indicates that it is outdated since support for the RISC-V V extension...

Hello, Brief background: We are trying to support 64 bit pointers in RISCV 32 bit backend http://lists.llvm.org/pipermail/llvm-dev/2019-June/132805.html To pass the legalizer we plan to break the 64 bit GlobalAddress into 32 bit GlobalAddress having the other 32 bit glued to the node. We could not find a direct way to convert the 64 bit GlobalAddress Node into a 32 bit n...