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Craig Topper via llvm-dev

2017-Jul-14 17:29 UTC

[llvm-dev] error:Ran out of lanemask bits to represent subregister

Do your 32768 registers also have sub registers?

I can't tell you exactly what to change. I'm not familiar with the code.
I
would just be running grep or something.

~Craig

On Fri, Jul 14, 2017 at 10:23 AM, hameeza ahmed <hahmed2305 at gmail.com>
wrote:
> Thank you so much. I think there is no issue with my definitions since i
> have to use larger registers i.e 65536 bit register made from 2 32768
> registers.
> I have seen your mentioned code files. But it looks difficult what to
> change.
> Could you please specify exactly where to make changes??
>
> Thank You
>
> On Fri, Jul 14, 2017 at 10:16 PM, Craig Topper <craig.topper at
gmail.com>
> wrote:
>
>> This error indicates that its trying to create a lane mask larger than
32
>> bits. Without seeing all of your subregister definitions I can't
tell if
>> that's correct of if there's something wrong with your register
definitions.
>>
>> If it is correct then you need to change all the associated LaneMask
code
>> in CodeGenRegisters.cpp, include/llvm/MC/LaneBitMask.h and probably
>> elsewhere to use a larger type than "unsigned" or
"uint32_t".
>>
>> ~Craig
>>
>> On Fri, Jul 14, 2017 at 10:09 AM, Tim Northover <t.p.northover at
gmail.com>
>> wrote:
>>
>>> Your first post was 6 hours ago and you've pinged it twice.
That's too
>>> frequent, the generally accepted ping rate on llvm lists is once
per week.
>>>
>>> Tim.
>>>
>>> On Jul 14, 2017 1:07 PM, "hameeza ahmed via llvm-dev"
<
>>> llvm-dev at lists.llvm.org> wrote:
>>>
>>>> please tell me how to solve this lanemask bits issue?
>>>>
>>>> how to increase lanemask bits?
>>>>
>>>> On Fri, Jul 14, 2017 at 8:33 PM, hameeza ahmed <hahmed2305
at gmail.com>
>>>> wrote:
>>>>
>>>>>
>>>>> Hello,
>>>>> i am trying to construct a register of size 65536 bit by
combining 2
>>>>> registers of 32768 bits. both the 32768 bit registers are
different so i
>>>>> have to use the following method
>>>>>
>>>>> let SubRegIndices = [sub_32768bit, sub_32768bit_hi],
CoveredBySubRegs
>>>>> = 1 in
>>>>>
>>>>> but i am getting following error..
>>>>>
>>>>> error:Ran out of lanemask bits to represent subregister
>>>>> sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit
>>>>>
>>>>> now how to increase lanemask bits? what changes are
required
>>>>> in IntrinsicEmitter.cpp file??
>>>>>
>>>>> Please reply.
>>>>>
>>>>>
>>>>>
>>>>
>>>> _______________________________________________
>>>> LLVM Developers mailing list
>>>> llvm-dev at lists.llvm.org
>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>
>>>>
>>
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hameeza ahmed via llvm-dev

2017-Jul-14 17:36 UTC

head link

[llvm-dev] error:Ran out of lanemask bits to represent subregister

The code file is attached here.

Kindly check it.

On Fri, Jul 14, 2017 at 10:29 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> Do your 32768 registers also have sub registers?
>
> I can't tell you exactly what to change. I'm not familiar with the
code. I
> would just be running grep or something.
>
> ~Craig
>
> On Fri, Jul 14, 2017 at 10:23 AM, hameeza ahmed <hahmed2305 at
gmail.com>
> wrote:
>
>> Thank you so much. I think there is no issue with my definitions since
i
>> have to use larger registers i.e 65536 bit register made from 2 32768
>> registers.
>> I have seen your mentioned code files. But it looks difficult what to
>> change.
>> Could you please specify exactly where to make changes??
>>
>> Thank You
>>
>> On Fri, Jul 14, 2017 at 10:16 PM, Craig Topper <craig.topper at
gmail.com>
>> wrote:
>>
>>> This error indicates that its trying to create a lane mask larger
than
>>> 32 bits. Without seeing all of your subregister definitions I
can't tell if
>>> that's correct of if there's something wrong with your
register definitions.
>>>
>>> If it is correct then you need to change all the associated
LaneMask
>>> code in CodeGenRegisters.cpp, include/llvm/MC/LaneBitMask.h and
probably
>>> elsewhere to use a larger type than "unsigned" or
"uint32_t".
>>>
>>> ~Craig
>>>
>>> On Fri, Jul 14, 2017 at 10:09 AM, Tim Northover <t.p.northover
at gmail.com
>>> > wrote:
>>>
>>>> Your first post was 6 hours ago and you've pinged it twice.
That's too
>>>> frequent, the generally accepted ping rate on llvm lists is
once per week.
>>>>
>>>> Tim.
>>>>
>>>> On Jul 14, 2017 1:07 PM, "hameeza ahmed via llvm-dev"
<
>>>> llvm-dev at lists.llvm.org> wrote:
>>>>
>>>>> please tell me how to solve this lanemask bits issue?
>>>>>
>>>>> how to increase lanemask bits?
>>>>>
>>>>> On Fri, Jul 14, 2017 at 8:33 PM, hameeza ahmed
<hahmed2305 at gmail.com>
>>>>> wrote:
>>>>>
>>>>>>
>>>>>> Hello,
>>>>>> i am trying to construct a register of size 65536 bit
by combining 2
>>>>>> registers of 32768 bits. both the 32768 bit registers
are different so i
>>>>>> have to use the following method
>>>>>>
>>>>>> let SubRegIndices = [sub_32768bit, sub_32768bit_hi],
CoveredBySubRegs
>>>>>> = 1 in
>>>>>>
>>>>>> but i am getting following error..
>>>>>>
>>>>>> error:Ran out of lanemask bits to represent subregister
>>>>>> sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit
>>>>>>
>>>>>> now how to increase lanemask bits? what changes are
required
>>>>>> in IntrinsicEmitter.cpp file??
>>>>>>
>>>>>> Please reply.
>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> LLVM Developers mailing list
>>>>> llvm-dev at lists.llvm.org
>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>>
>>>>>
>>>
>>
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let Namespace = "R" in {
def sub_32bit     : SubRegIndex<32>;
def sub_64bit      : SubRegIndex<64>;
def sub_128bit     : SubRegIndex<128>;
def sub_256bit     : SubRegIndex<256>;
def sub_512bit     : SubRegIndex<512>;
def sub_1024bit    : SubRegIndex<1024>;
def sub_2048bit    : SubRegIndex<2048>;
def sub_2048bit_hi : SubRegIndex<2048, 2048>;
def sub_4096bit    : SubRegIndex<4096>;
def sub_4096bit_hi : SubRegIndex<4096, 4096>;
def sub_8192bit    : SubRegIndex<8192>;
def sub_8192bit_hi : SubRegIndex<8192, 8192>;
def sub_16384bit    : SubRegIndex<16384>;
def sub_16384bit_hi : SubRegIndex<16384, 16384>;
def sub_32768bit    : SubRegIndex<32768>;
def sub_32768bit_hi : SubRegIndex<32768, 32768>;


}

foreach J = 0-31 in { 
foreach I = 0-511 in
 { 
def R_#J#_REG32b_#I : R_CLASS<"R_" #J# "R32b_"#I, I>,
DwarfRegNum<[I]>; }


let SubRegIndices = [sub_32bit] in {
    foreach I = 0-255 in
        def R_#J#_REG64b_#I : R_CLASS<"R_"#J#"_R64b_"#I,
I, [!cast<R_CLASS>("R_"#J#"_REG32b_"#I)]>;
}

let SubRegIndices = [sub_64bit] in {
    foreach I = 0-127 in
        def R_#J#_REG128b_#I :
R_CLASS<"R_"#J#"_R128b_"#I, I,
[!cast<R_CLASS>("R_"#J#"_REG64b_"#I)]>;
}

let SubRegIndices = [sub_128bit] in {
    foreach I = 0-63 in
        def R_#J#_REG256b_#I :
R_CLASS<"R_"#J#"_R256b_"#I, I,
[!cast<R_CLASS>("R_"#J#"_REG128b_"#I)]>;
}    

let SubRegIndices = [sub_256bit] in {
    foreach I = 0-31 in
        def R_#J#_REG512b_#I :
R_CLASS<"R_"#J#"_R512b_"#I, I,
[!cast<R_CLASS>("R_"#J#"_REG256b_"#I)]>;
}        

let SubRegIndices = [sub_512bit], CoveredBySubRegs = 1 in {
    foreach I = 0-15 in
        def R_#J#_REG1024b_#I :
R_CLASS<"R_"#J#"_R1024b_"#I, I,
[!cast<R_CLASS>("R_"#J#"_REG512b_"#I)]>;
}        

let SubRegIndices = [sub_1024bit] in {
    foreach I = 0-7 in
        def R_#J#_REG2048b_#I :
R_CLASS<"R_"#J#"_R2048b_"#I, I,
[!cast<R_CLASS>("R_"#J#"_REG1024b_"#I)]>;
}

} //end of J loop

let SubRegIndices = [sub_2048bit, sub_2048bit_hi], CoveredBySubRegs = 1 in {
    foreach I = 0-7 in
     {  def R_0_1_REG4Kb_#I : R_CLASS<"R_0_1_R4Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_0_REG2048b_"#I),
!cast<R_CLASS>("R_1_REG2048b_"#I)]>;
        def R_2_3_REG4Kb_#I : R_CLASS<"R_2_3_R4Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_2_REG2048b_"#I),
!cast<R_CLASS>("R_3_REG2048b_"#I)]>;
        def R_4_5_REG4Kb_#I : R_CLASS<"R_4_5_R4Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_4_REG2048b_"#I),
!cast<R_CLASS>("R_5_REG2048b_"#I)]>;
        def R_6_7_REG4Kb_#I : R_CLASS<"R_6_7_R4Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_6_REG2048b_"#I),
!cast<R_CLASS>("R_7_REG2048b_"#I)]>;
        def R_8_9_REG4Kb_#I : R_CLASS<"R_8_9_R4Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_8_REG2048b_"#I),
!cast<R_CLASS>("R_9_REG2048b_"#I)]>;
        
        def R_10_11_REG4Kb_#I : R_CLASS<"R_10_11_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_10_REG2048b_"#I),
!cast<R_CLASS>("R_11_REG2048b_"#I)]>;
        def R_12_13_REG4Kb_#I : R_CLASS<"R_12_13_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_12_REG2048b_"#I),
!cast<R_CLASS>("R_13_REG2048b_"#I)]>;
        def R_14_15_REG4Kb_#I : R_CLASS<"R_14_15_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_14_REG2048b_"#I),
!cast<R_CLASS>("R_15_REG2048b_"#I)]>;
        def R_16_17_REG4Kb_#I : R_CLASS<"R_16_17_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_16_REG2048b_"#I),
!cast<R_CLASS>("R_17_REG2048b_"#I)]>;
        def R_18_19_REG4Kb_#I : R_CLASS<"R_18_19_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_18_REG2048b_"#I),
!cast<R_CLASS>("R_19_REG2048b_"#I)]>;
        
        def R_20_21_REG4Kb_#I : R_CLASS<"R_20_21_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_20_REG2048b_"#I),
!cast<R_CLASS>("R_21_REG2048b_"#I)]>;
        def R_22_23_REG4Kb_#I : R_CLASS<"R_22_23_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_22_REG2048b_"#I),
!cast<R_CLASS>("R_23_REG2048b_"#I)]>;
        def R_24_25_REG4Kb_#I : R_CLASS<"R_24_25_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_24_REG2048b_"#I),
!cast<R_CLASS>("R_25_REG2048b_"#I)]>;
        def R_26_27_REG4Kb_#I : R_CLASS<"R_26_27_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_26_REG2048b_"#I),
!cast<R_CLASS>("R_27_REG2048b_"#I)]>;
        def R_28_29_REG4Kb_#I : R_CLASS<"R_28_29_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_28_REG2048b_"#I),
!cast<R_CLASS>("R_29_REG2048b_"#I)]>;
        def R_30_31_REG4Kb_#I : R_CLASS<"R_30_31_R4Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_30_REG2048b_"#I),
!cast<R_CLASS>("R_31_REG2048b_"#I)]>;



}

}
let SubRegIndices = [sub_4096bit, sub_4096bit_hi], CoveredBySubRegs = 1 in {
    foreach I = 0-7 in
  {     def R_0_1_2_3_REG8Kb_#I : R_CLASS<"R_0_1_2_3_R8Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_0_1_REG4Kb_"#I),
!cast<R_CLASS>("R_2_3_REG4Kb_"#I)]>;
        def R_4_5_6_7_REG8Kb_#I : R_CLASS<"R_4_5_6_7_R8Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_4_5_REG4Kb_"#I),
!cast<R_CLASS>("R_6_7_REG4Kb_"#I)]>;
        def R_8_9_10_11_REG8Kb_#I : R_CLASS<"R_8_9_10_11_R8Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_8_9_REG4Kb_"#I),
!cast<R_CLASS>("R_10_11_REG4Kb_"#I)]>;
        def R_12_13_14_15_REG8Kb_#I :
R_CLASS<"R_12_13_14_15_R8Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_12_13_REG4Kb_"#I),
!cast<R_CLASS>("R_14_15_REG4Kb_"#I)]>;
        
        def R_16_17_18_19_REG8Kb_#I :
R_CLASS<"R_16_17_18_19_R8Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_16_17_REG4Kb_"#I),
!cast<R_CLASS>("R_18_19_REG4Kb_"#I)]>;
        def R_20_21_22_23_REG8Kb_#I :
R_CLASS<"R_20_21_22_23_R8Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_20_21_REG4Kb_"#I),
!cast<R_CLASS>("R_22_23_REG4Kb_"#I)]>;
        def R_24_25_26_27_REG8Kb_#I :
R_CLASS<"R_24_25_26_27_R8Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_24_25_REG4Kb_"#I),
!cast<R_CLASS>("R_26_27_REG4Kb_"#I)]>;
        def R_28_29_30_31_REG8Kb_#I :
R_CLASS<"R_28_29_30_31_R8Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_28_29_REG4Kb_"#I),
!cast<R_CLASS>("R_30_31_REG4Kb_"#I)]>;

}
}


let SubRegIndices = [sub_8192bit, sub_8192bit_hi], CoveredBySubRegs = 1 in {
    foreach I = 0-7 in
     {   def R_0_1_2_3_4_5_6_7_REG16Kb_#I :
R_CLASS<"R_0_1_2_3_4_5_6_7_R16Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_0_1_2_3_REG8Kb_"#I),
!cast<R_CLASS>("R_4_5_6_7_REG8Kb_"#I)]>;
        def R_8_9_10_11_12_13_14_15_REG16Kb_#I :
R_CLASS<"R_8_9_10_11_12_13_14_15_R16Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_8_9_10_11_REG8Kb_"#I),
!cast<R_CLASS>("R_12_13_14_15_REG8Kb_"#I)]>;
        def R_16_17_18_19_20_21_22_23_REG16Kb_#I :
R_CLASS<"R_16_17_18_19_20_21_22_23_R16Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_16_17_18_19_REG8Kb_"#I),
!cast<R_CLASS>("R_20_21_22_23_REG8Kb_"#I)]>;
        def R_24_25_26_27_28_29_30_31_REG16Kb_#I :
R_CLASS<"R_24_25_26_27_28_29_30_31_R16Kb_"#I, !shl(I,2),
[!cast<R_CLASS>("R_24_25_26_27_REG8Kb_"#I),
!cast<R_CLASS>("R_28_29_30_31_REG8Kb_"#I)]>;

}
}

let SubRegIndices = [sub_16384bit, sub_16384bit_hi], CoveredBySubRegs = 1 in {
    foreach I = 0-7 in
       { def R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_REG32Kb_#I :
R_CLASS<"R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_R32Kb_"#I,
!shl(I,2), [!cast<R_CLASS>("R_0_1_2_3_4_5_6_7_REG16Kb_"#I),
!cast<R_CLASS>("R_8_9_10_11_12_13_14_15_REG16Kb_"#I)]>;
        def R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG32Kb_#I :
R_CLASS<"R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_R32Kb_"#I,
!shl(I,2),
[!cast<R_CLASS>("R_16_17_18_19_20_21_22_23_REG16Kb_"#I),
!cast<R_CLASS>("R_24_25_26_27_28_29_30_31_REG16Kb_"#I)]>;
        

}
}

let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = 1 in {
    foreach I = 0-7 in
        def
R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG64Kb_#I
:
R_CLASS<"R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_R64Kb_"#I,
!shl(I,2),
[!cast<R_CLASS>("R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_REG32Kb_"#I),
!cast<R_CLASS>("R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG32Kb_"#I)]>;
       
}

Craig Topper via llvm-dev

2017-Jul-14 18:32 UTC

head link

[llvm-dev] error:Ran out of lanemask bits to represent subregister

I've commited r308042 to make it a little easier to change the underlying
type in the LaneBitmask class. With that change you might not need to touch
CodeGenRegisters.cpp now. But I can't promise anything.

~Craig

On Fri, Jul 14, 2017 at 10:36 AM, hameeza ahmed <hahmed2305 at gmail.com>
wrote:
> The code file is attached here.
>
> Kindly check it.
>
> On Fri, Jul 14, 2017 at 10:29 PM, Craig Topper <craig.topper at
gmail.com>
> wrote:
>
>> Do your 32768 registers also have sub registers?
>>
>> I can't tell you exactly what to change. I'm not familiar with
the code.
>> I would just be running grep or something.
>>
>> ~Craig
>>
>> On Fri, Jul 14, 2017 at 10:23 AM, hameeza ahmed <hahmed2305 at
gmail.com>
>> wrote:
>>
>>> Thank you so much. I think there is no issue with my definitions
since i
>>> have to use larger registers i.e 65536 bit register made from 2
32768
>>> registers.
>>> I have seen your mentioned code files. But it looks difficult what
to
>>> change.
>>> Could you please specify exactly where to make changes??
>>>
>>> Thank You
>>>
>>> On Fri, Jul 14, 2017 at 10:16 PM, Craig Topper <craig.topper at
gmail.com>
>>> wrote:
>>>
>>>> This error indicates that its trying to create a lane mask
larger than
>>>> 32 bits. Without seeing all of your subregister definitions I
can't tell if
>>>> that's correct of if there's something wrong with your
register definitions.
>>>>
>>>> If it is correct then you need to change all the associated
LaneMask
>>>> code in CodeGenRegisters.cpp, include/llvm/MC/LaneBitMask.h and
probably
>>>> elsewhere to use a larger type than "unsigned" or
"uint32_t".
>>>>
>>>> ~Craig
>>>>
>>>> On Fri, Jul 14, 2017 at 10:09 AM, Tim Northover <
>>>> t.p.northover at gmail.com> wrote:
>>>>
>>>>> Your first post was 6 hours ago and you've pinged it
twice. That's too
>>>>> frequent, the generally accepted ping rate on llvm lists is
once per week.
>>>>>
>>>>> Tim.
>>>>>
>>>>> On Jul 14, 2017 1:07 PM, "hameeza ahmed via
llvm-dev" <
>>>>> llvm-dev at lists.llvm.org> wrote:
>>>>>
>>>>>> please tell me how to solve this lanemask bits issue?
>>>>>>
>>>>>> how to increase lanemask bits?
>>>>>>
>>>>>> On Fri, Jul 14, 2017 at 8:33 PM, hameeza ahmed
<hahmed2305 at gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>>
>>>>>>> Hello,
>>>>>>> i am trying to construct a register of size 65536
bit by combining 2
>>>>>>> registers of 32768 bits. both the 32768 bit
registers are different so i
>>>>>>> have to use the following method
>>>>>>>
>>>>>>> let SubRegIndices = [sub_32768bit,
sub_32768bit_hi],
>>>>>>> CoveredBySubRegs = 1 in
>>>>>>>
>>>>>>> but i am getting following error..
>>>>>>>
>>>>>>> error:Ran out of lanemask bits to represent
subregister
>>>>>>> sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit
>>>>>>>
>>>>>>> now how to increase lanemask bits? what changes are
required
>>>>>>> in IntrinsicEmitter.cpp file??
>>>>>>>
>>>>>>> Please reply.
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> LLVM Developers mailing list
>>>>>> llvm-dev at lists.llvm.org
>>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>>>
>>>>>>
>>>>
>>>
>>
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hameeza ahmed via llvm-dev

2017-Jul-18 10:58 UTC

head link

[llvm-dev] error:Ran out of lanemask bits to represent subregister

still getting the same error:
error:Ran out of lanemask bits to represent subregister
sub_32768bit_hi_then_sub_16384bit_hi_then_sub_8192bit_hi_then
_sub_4096bit_hi_then_sub_2048bit_hi_then_sub_32bit_hi_then

Can someone please help??



On Sat, Jul 15, 2017 at 12:57 AM, Craig Topper <craig.topper at gmail.com>
wrote:
> There's probably a call to Log2_32 a few lines down from that should be
> Log2_64 now. And the static assert should be fixed to say 8 instead of 4.
>
> ~Craig
>
> On Fri, Jul 14, 2017 at 12:20 PM, hameeza ahmed <hahmed2305 at
gmail.com>
> wrote:
>
>> i even did the changes mentioned here;
>>
>> https://github.com/llvm-mirror/llvm/commit/c68f8f2fd3c004e60
>> e958761b00a9ae4bce97e2d
>>
>> but not solved
>>
>> On Sat, Jul 15, 2017 at 12:06 AM, hameeza ahmed <hahmed2305 at
gmail.com>
>> wrote:
>>
>>> As you said i made;
>>> typedef uint64_t Type;
>>> in include/llvm/MC/LaneBitmask.h
>>> but now getting this error;
>>>
>>> utils/TableGen/CodeGenRegisters.cpp:1258:9: error:
>>>       static_assert failed "Change Log2_32 to a proper
one"
>>>         static_assert(sizeof(Composite->LaneMask.getAsInteger())
== 4,
>>>
>>> On Fri, Jul 14, 2017 at 11:56 PM, Craig Topper <craig.topper at
gmail.com>
>>> wrote:
>>>
>>>> I can tell you that you shoudl start by changing the Type field
in
>>>> include/llvm/MC/LaneBitmask.h from unsigned to uint64_t.
>>>>
>>>> ~Craig
>>>>
>>>> On Fri, Jul 14, 2017 at 11:56 AM, Craig Topper <craig.topper
at gmail.com>
>>>> wrote:
>>>>
>>>>> I'm sorry, but I don't have any bandwidth to make
the changes for you
>>>>> or thoroughly investigate what the changes are.
>>>>>
>>>>> ~Craig
>>>>>
>>>>> On Fri, Jul 14, 2017 at 11:48 AM, hameeza ahmed
<hahmed2305 at gmail.com>
>>>>> wrote:
>>>>>
>>>>>> sorry to disturb. but with further testing getting that
error again.
>>>>>> have you make some patch? how can i fix it?
>>>>>>
>>>>>> On Fri, Jul 14, 2017 at 11:44 PM, hameeza ahmed
<hahmed2305 at gmail.com
>>>>>> > wrote:
>>>>>>
>>>>>>> I rechecked my code there was some typo. i
corrected it now no lane
>>>>>>> bitmask errors.
>>>>>>>
>>>>>>> Thank You again
>>>>>>>
>>>>>>> On Fri, Jul 14, 2017 at 11:32 PM, Craig Topper <
>>>>>>> craig.topper at gmail.com> wrote:
>>>>>>>
>>>>>>>> I've commited r308042 to make it a little
easier to change the
>>>>>>>> underlying type in the LaneBitmask class. With
that change you might not
>>>>>>>> need to touch CodeGenRegisters.cpp now. But I
can't promise anything.
>>>>>>>>
>>>>>>>> ~Craig
>>>>>>>>
>>>>>>>> On Fri, Jul 14, 2017 at 10:36 AM, hameeza ahmed
<
>>>>>>>> hahmed2305 at gmail.com> wrote:
>>>>>>>>
>>>>>>>>> The code file is attached here.
>>>>>>>>>
>>>>>>>>> Kindly check it.
>>>>>>>>>
>>>>>>>>> On Fri, Jul 14, 2017 at 10:29 PM, Craig
Topper <
>>>>>>>>> craig.topper at gmail.com> wrote:
>>>>>>>>>
>>>>>>>>>> Do your 32768 registers also have sub
registers?
>>>>>>>>>>
>>>>>>>>>> I can't tell you exactly what to
change. I'm not familiar with
>>>>>>>>>> the code. I would just be running grep
or something.
>>>>>>>>>>
>>>>>>>>>> ~Craig
>>>>>>>>>>
>>>>>>>>>> On Fri, Jul 14, 2017 at 10:23 AM,
hameeza ahmed <
>>>>>>>>>> hahmed2305 at gmail.com> wrote:
>>>>>>>>>>
>>>>>>>>>>> Thank you so much. I think there is
no issue with my definitions
>>>>>>>>>>> since i have to use larger
registers i.e 65536 bit register made from 2
>>>>>>>>>>> 32768 registers.
>>>>>>>>>>> I have seen your mentioned code
files. But it looks difficult
>>>>>>>>>>> what to change.
>>>>>>>>>>> Could you please specify exactly
where to make changes??
>>>>>>>>>>>
>>>>>>>>>>> Thank You
>>>>>>>>>>>
>>>>>>>>>>> On Fri, Jul 14, 2017 at 10:16 PM,
Craig Topper <
>>>>>>>>>>> craig.topper at gmail.com>
wrote:
>>>>>>>>>>>
>>>>>>>>>>>> This error indicates that its
trying to create a lane mask
>>>>>>>>>>>> larger than 32 bits. Without
seeing all of your subregister definitions I
>>>>>>>>>>>> can't tell if that's
correct of if there's something wrong with your
>>>>>>>>>>>> register definitions.
>>>>>>>>>>>>
>>>>>>>>>>>> If it is correct then you need
to change all the associated
>>>>>>>>>>>> LaneMask code in
CodeGenRegisters.cpp, include/llvm/MC/LaneBitMask.h and
>>>>>>>>>>>> probably elsewhere to use a
larger type than "unsigned" or "uint32_t".
>>>>>>>>>>>>
>>>>>>>>>>>> ~Craig
>>>>>>>>>>>>
>>>>>>>>>>>> On Fri, Jul 14, 2017 at 10:09
AM, Tim Northover <
>>>>>>>>>>>> t.p.northover at gmail.com>
wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>> Your first post was 6 hours
ago and you've pinged it twice.
>>>>>>>>>>>>> That's too frequent,
the generally accepted ping rate on llvm lists is once
>>>>>>>>>>>>> per week.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Tim.
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Jul 14, 2017 1:07 PM,
"hameeza ahmed via llvm-dev" <
>>>>>>>>>>>>> llvm-dev at
lists.llvm.org> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>>> please tell me how to
solve this lanemask bits issue?
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> how to increase
lanemask bits?
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> On Fri, Jul 14, 2017 at
8:33 PM, hameeza ahmed <
>>>>>>>>>>>>>> hahmed2305 at
gmail.com> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Hello,
>>>>>>>>>>>>>>> i am trying to
construct a register of size 65536 bit by
>>>>>>>>>>>>>>> combining 2
registers of 32768 bits. both the 32768 bit registers are
>>>>>>>>>>>>>>> different so i have
to use the following method
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> let SubRegIndices =
[sub_32768bit, sub_32768bit_hi],
>>>>>>>>>>>>>>> CoveredBySubRegs =
1 in
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> but i am getting
following error..
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> error:Ran out of
lanemask bits to represent subregister
>>>>>>>>>>>>>>>
sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> now how to increase
lanemask bits? what changes are required
>>>>>>>>>>>>>>> in
IntrinsicEmitter.cpp file??
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Please reply.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
_______________________________________________
>>>>>>>>>>>>>> LLVM Developers mailing
list
>>>>>>>>>>>>>> llvm-dev at
lists.llvm.org
>>>>>>>>>>>>>>
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
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llvm dev - Jul 2017 - error:Ran out of lanemask bits to represent subregister

[llvm-dev] error:Ran out of lanemask bits to represent subregister

[llvm-dev] error:Ran out of lanemask bits to represent subregister

[llvm-dev] error:Ran out of lanemask bits to represent subregister

[llvm-dev] error:Ran out of lanemask bits to represent subregister